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ORCIDMatthew J. Thazhuthaveetil
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2020 – today
- 2024
[c20]Shilpa Babalad
, Shirish K. Shevade, Matthew Jacob Thazhuthaveetil, R. Govindarajan:
Tile Size and Loop Order Selection using Machine Learning for Multi-/Many-Core Architectures. ICS 2024: 388-399
2010 – 2019
- 2014
- [c19]Sreepathi Pai, R. Govindarajan, Matthew J. Thazhuthaveetil:
Preemptive thread block scheduling with online structural runtime prediction for concurrent GPGPU kernels. PACT 2014: 483-484 - [i1]Sreepathi Pai, R. Govindarajan, Matthew J. Thazhuthaveetil:
Preemptive Thread Block Scheduling with Online Structural Runtime Prediction for Concurrent GPGPU Kernels. CoRR abs/1406.6037 (2014) - 2013
- [c18]Sreepathi Pai, Matthew J. Thazhuthaveetil, R. Govindarajan:
Improving GPGPU concurrency with elastic kernels. ASPLOS 2013: 407-418 - 2012
- [c17]Sreepathi Pai, R. Govindarajan, Matthew J. Thazhuthaveetil:
Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme. PACT 2012: 33-42 - [c16]Raghu Prabhakar, R. Govindarajan, Matthew J. Thazhuthaveetil:
CUDA-For-Clusters: A System for Efficient Execution of CUDA Kernels on Multi-core Clusters. Euro-Par 2012: 415-426
2000 – 2009
- 2009
- [c15]Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil:
Software Pipelined Execution of Stream Programs on GPUs. CGO 2009: 200-209 - [c14]Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil:
Synergistic execution of stream programs on multicores with accelerators. LCTES 2009: 99-108 - 2008
- [j9]V. Santhosh Kumar, Ravi S. Nanjundiah, Matthew J. Thazhuthaveetil, R. Govindarajan:
Impact of message compression on the scalability of an atmospheric modeling application on clusters. Parallel Comput. 34(1): 1-16 (2008) - 2007
- [c13]Kapil Vaswani, Matthew J. Thazhuthaveetil, Y. N. Srikant, P. J. Joseph:
Microarchitecture Sensitive Empirical Models for Compiler Optimizations. CGO 2007: 131-143 - 2006
- [c12]P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil:
Construction and use of linear regression models for processor performance analysis. HPCA 2006: 99-108 - [c11]V. Santhosh Kumar, Matthew J. Thazhuthaveetil, R. Govindarajan:
Exploiting programmable network interfaces for parallel query execution in workstation clusters. IPDPS 2006 - [c10]P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil:
A Predictive Performance Model for Superscalar Processors. MICRO 2006: 161-170 - 2005
- [c9]Kapil Vaswani, Matthew J. Thazhuthaveetil, Y. N. Srikant:
A Programmable Hardware Path Profiler. CGO 2005: 217-228 - [c8]V. Santhosh Kumar, Matthew J. Thazhuthaveetil, R. Govindarajan:
Offloading Bloom Filter Operations to Network Processor for Parallel Query Processing in Cluster of Workstations. HiPC 2005: 170-179 - 2001
- [c7]Subramania Sharma, Matthew Thazhuthaveetil:
TWLinuX : Operating System Support for Optimistic Parallel Discrete Event Simulation. HiPC 2001: 262-271
1990 – 1999
- 1995
- [j8]Mazin S. Yousif, Matthew Thazhuthaveetil, Chita R. Das:
Cache Coherence in Multiprocessors: A Survey. Adv. Comput. 40: 127-179 (1995) - 1994
- [j7]K. V. Subramaniam, Matthew J. Thazhuthaveetil:
Design of an MS-DOS PC program profiler. Microprocess. Microsystems 18(5): 261-269 (1994) - [j6]Mazin S. Yousif, Chita R. Das, Matthew J. Thazhuthaveetil:
A Cache coherence protocol for MIN-based multiprocessors. J. Supercomput. 8(2): 163-185 (1994) - 1993
- [c6]Mazin S. Yousif, Chita R. Das, Matthew Thazhuthaveetil:
A Cache Coherence Protocol for MIN-Based Multprocessors With Limited Inclusion. ICPP (1) 1993: 254-257 - 1991
- [j5]Matthew J. Thazhuthaveetil, Anish V. Shah:
Parallel hough transform algorithm performance. Image Vis. Comput. 9(2): 88-92 (1991) - [c5]Mazin S. Algudady, Chita R. Das, Matthew Thazhuthaveetil:
A Cache-Based Checkpointing Scheme for MIN-Based Multiprocessors. ICPP (1) 1991: 497-500 - [c4]Lizyamma Kurian, Matthew Thazhuthaveetil:
Effect of Hot Spots on Multiprocessor Systems Using Circuit Switched Interconnection Networks. ICPP (1) 1991: 554-557 - 1990
- [j4]Chita R. Das, Jeffrey T. Kreulen, Matthew Thazhuthaveetil, Laxmi N. Bhuyan:
Dependability Modeling for Multiprocessors. Computer 23(10): 7-19 (1990) - [j3]Jeffrey T. Kreulen, Matthew J. Thazhuthaveetil:
Application-dependent simulation of microprocessor-based multiprocessors. Microprocess. Microsystems 14(7): 467-473 (1990) - [c3]Robert L. Lesher, Matthew Thazhuthaveetil:
Hotspot Contention in Non-Blocking Multistage Interconnection Networks. ICPP (1) 1990: 401-404 - [c2]Mazin S. Algudady, Chita R. Das, Matthew Thazhuthaveetil:
A write update cache coherence protocol for MIN-based multiprocessors with accessibility-based split caches. SC 1990: 544-553
1980 – 1989
- 1987
- [j2]Andrew R. Pleszkun, Matthew Thazhuthaveetil:
The Architecture of Lisp Machines. Computer 20(3): 35-44 (1987) - [j1]Matthew Thazhuthaveetil, Andrew R. Pleszkun:
On the Structural Locality of Reference in LISP List Access Streams. Inf. Process. Lett. 26(2): 105-110 (1987) - 1986
- [c1]Andrew R. Pleszkun, Matthew Thazhuthaveetil:
An Architecture for Efficient Lisp List Access. ISCA 1986: 191-198
Coauthor Index
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