Verification and Evaluation of Computer and Communication Systems - 17th International Conference, VECoS 2024, Djerba, Tunisia, October 16-18, 2024, Proceedings (Springer, 2025)

Preface to the VECoS 2020 & 2021 special issue of ISSE. - Barkaoui, Kamel; Hedia, Belgacem Ben (Innov. Syst. Softw. Eng., 2024)

Verification and Evaluation of Computer and Communication Systems - 16th International Conference, VECoS 2023, Marrakech, Morocco, October 18-20, 2023, Proceedings (Springer, 2024)

Formal modeling and verification for amplification timing anomalies in the superscalar TriCore architecture. - Binder, Benjamin; Asavoae, Mihail; Brandner, Florian; Hedia, Belgacem Ben; Jan, Mathieu (Int. J. Softw. Tools Technol. Transf., 2022)

The Role of Causality in a Formal Definition of Timing Anomalies. - Binder, Benjamin; Asavoae, Mihail; Brandner, Florian; Hedia, Belgacem Ben; Jan, Mathieu (2022)

Is This Still Normal? Putting Definitions of Timing Anomalies to the Test. - Binder, Benjamin; Asavoae, Mihail; Hedia, Belgacem Ben; Brandner, Florian; Jan, Mathieu (2021)

Scalable Detection of Amplification Timing Anomalies for the Superscalar TriCore Architecture. - Binder, Benjamin; Asavoae, Mihail; Brandner, Florian; Hedia, Belgacem Ben; Jan, Mathieu (2020)

Verification and Evaluation of Computer and Communication Systems - 14th International Conference, VECoS 2020, Xi'an, China, October 26-27, 2020, Proceedings (Springer, 2020)

Towards Formal Co-validation of Hardware and Software Timing Models of CPSs. - Asavoae, Mihail; Haur, Imane; Jan, Mathieu; Hedia, Belgacem Ben; Schoeberl, Martin (2019)

TT-BIP: using correct-by-design BIP approach for modelling real-time system with time-triggered paradigm. - Guesmi, Hela; Hedia, Belgacem Ben; Bliudze, Simon; Bensalem, Saddek; Nabec, Briag Le (Innov. Syst. Softw. Eng., 2018)

QuaRTOS-DSE: A Tool for Design Space Exploration of Embedded Real-Time System. - Nabec, Briag Le; Hedia, Belgacem Ben; Babau, Jean-Philippe (2018)

Formal Executable Models for Automatic Detection of Timing Anomalies. - Asavoae, Mihail; Hedia, Belgacem Ben; Jan, Mathieu (2018)

TT-BIP: Using Correct-by-Design BIP Approach for Modelling Real-Time System with Time-Triggered Paradigm. - Guesmi, Hela; Hedia, Belgacem Ben; Bliudze, Simon; Bensalem, Saddek; Nabec, Briag Le (2017)

Modeling legacy code with BIP: how to reduce the gap between formal description and real-time implementation. - Nabec, Briag Le; Hedia, Belgacem Ben; Babau, Jean-Philippe; Jan, Mathieu; Guesmi, Hela (2016)

Poster Abstract: Towards Correct Transformation: From High-Level Models to Time-Triggered Implementations. - Guesmi, Hela; Hedia, Belgacem Ben; Jan, Mathieu; Bliudze, Simon; Bensalem, Saddek (2016)

Towards an Ultra-lightweight Cryptosystem for IoT. - Omrani, Tasnime; Sliman, Layth; Becheikh, Rabei; Belghith, Safya; Hedia, Belgacem Ben (2016)

State Space Reduction Strategie for Model Checking Concurrent C Programs. - Methni, Amira; Lemerre, Matthieu; Hedia, Belgacem Ben; Haddad, Serge; Barkaoui, Kamel (2015)

Proceedings of the 9th Workshop on Verification and Evaluation of Computer and Communication Systems, VECoS 2015, Bucharest, Romania, September 10-11, 2015. (CEUR-WS.org, 2015)

Specifying and Verifying Concurrent C Programs with TLA+. - Methni, Amira; Lemerre, Matthieu; Hedia, Belgacem Ben; Haddad, Serge; Barkaoui, Kamel (2014)

22nd International Conference on Real-Time Networks and Systems, RTNS '14, Versaille, France, October 8-10, 2014 (ACM, 2014)