Accuracy Improvement of Memory System Simulation for Modern Shared Memory Processor. - Kodama, Yuetsu; Odajima, Tetsuya; Asato, Akira; Sato, Mitsuhisa (2020)

Co-design for A64FX manycore processor and "Fugaku". - Sato, Mitsuhisa; Ishikawa, Yutaka; Tomita, Hirofumi; Kodama, Yuetsu; Odajima, Tetsuya; Tsuji, Miwako; Yashiro, Hisashi; Aoki, Masaki; Shida, Naoyuki; Miyoshi, Ikuo; Hirai, Kouichi; Furuya, Atsushi; et al. (2020)

Evaluation of the RIKEN Post-K Processor Simulator. - Kodama, Yuetsu; Odajima, Tetsuya; Asato, Akira; Sato, Mitsuhisa (CoRR, 2019)

A Case Study: Energy Efficient High Throughput Chip Multi-Processor Using Reduced-complexity Cores for Transaction Processing Workload. - Ando, Hisashige; Asato, Akira; Kawaba, Motoyuki; Okawara, Hideki; Walker, William W. (Inf. Media Technol., 2006)

Grid Service Platform: Design and Implementation of Grid Middleware for Telecom Carriers. - Shigeta, Soichi; Imamura, Nobutaka; Ueda, Haruyasu; Kobashi, Hiromichi; Murata, Miho; Yoshida, Taketoshi; Kubota, Atsushi; Asato, Akira; Kadooka, Yoshimasa (2006)

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. - Kubosawa, Hajime; Higaki, Naoshi; Ando, Satoshi; Takahashi, Hiromasa; Asada, Yoshimi; Anbutsu, Hideaki; Sato, Tomio; Sakate, Masato; Suga, Atsuhiro; Kimura, Michihide; Miyake, Hideo; Okano, Hiroshi; et al. (IEEE J. Solid State Circuits, 1999)

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications. - Kubosawa, Hajime; Takahashi, Hiromasa; Ando, Satoshi; Asada, Yoshimi; Asato, Akira; Suga, Atsuhiro; Kimura, Michihide; Higaki, Naoshi; Miyake, Hideo; Sato, Tomio; Anbutsu, Hideaki; Tsuda, Toshitaka; et al. (IEEE J. Solid State Circuits, 1998)

Architecture and Implementation of PIM/p. - Kumon, Kouichi; Asato, Akira; Arai, Susumu; Shinogi, Tsuyoshi; Hattori, Akira; Hatazawa, Hiroyoshi; Hirano, Kiyoshi (1992)