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Edoardo Fusella
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2010 – 2019
- 2019
- [j11]Edoardo Fusella, Mahdi Nikdast, Ian O'Connor, José Flich, Sudeep Pasricha:
Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications. ACM J. Emerg. Technol. Comput. Syst. 15(1): 1:1-1:2 (2019) - 2018
- [j10]Edoardo Fusella, Alessandro Cilardo:
Reducing Power Consumption of Lasers in Photonic NoCs through Application-Specific Mapping. ACM J. Emerg. Technol. Comput. Syst. 14(2): 23:1-23:11 (2018) - [j9]José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni:
Exploring manycore architectures for next-generation HPC systems through the MANGO approach. Microprocess. Microsystems 61: 154-170 (2018) - [j8]Edoardo Fusella, Alessandro Cilardo:
Lattice-Based Turn Model for Adaptive Routing. IEEE Trans. Parallel Distributed Syst. 29(5): 1117-1130 (2018) - [c10]Edoardo Fusella, Alessandro Cilardo:
Understanding turn models for adaptive routing: The modular approach. DATE 2018: 1477-1480 - [c9]Mirko Gagliardi, Edoardo Fusella, Alessandro Cilardo:
Improving Deep Learning with a customizable GPU-like FPGA-based accelerator. PRIME 2018: 273-276 - 2017
- [j7]Edoardo Fusella, José Flich, Alessandro Cilardo:
Path Setup for Hybrid NoC Architectures Exploiting Flooding and Standby. IEEE Trans. Parallel Distributed Syst. 28(5): 1403-1416 (2017) - [j6]Edoardo Fusella, Alessandro Cilardo:
H2ONoC: A Hybrid Optical-Electronic NoC Based on Hybrid Topology. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 330-343 (2017) - [c8]Edoardo Fusella:
A Deterministic Approach to Improve Inter-Domain Parallelism of Clustered MPSoC Interconnects. AINA Workshops 2017: 680-685 - [c7]José Flich, Alessandro Cilardo, Mario Kovaç, Rafael Tornero, Mirko Gagliardi, Edoardo Fusella, José Maria Martínez, Tomás Picornell:
Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration. PARCO 2017: 381-389 - 2016
- [j5]Alessandro Cilardo, Edoardo Fusella:
Design automation for application-specific on-chip interconnects: A survey. Integr. 52: 102-121 (2016) - [j4]Edoardo Fusella, Alessandro Cilardo:
Minimizing power loss in optical networks-on-chip through application-specific mapping. Microprocess. Microsystems 43: 4-13 (2016) - [j3]Edoardo Fusella, Alessandro Cilardo:
Crosstalk-Aware Automated Mapping for Optical Networks-on-Chip. ACM Trans. Embed. Comput. Syst. 16(1): 16:1-16:26 (2016) - [c6]Edoardo Fusella, Alessandro Cilardo:
PhoNoCMap: An application mapping tool for photonic networks-on-chip. DATE 2016: 289-292 - 2015
- [j2]Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo:
Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects. ACM Trans. Embed. Comput. Syst. 14(3): 57:1-57:24 (2015) - [c5]Edoardo Fusella, Alessandro Cilardo, Antonino Mazzeo:
Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip. FPL 2015: 1-2 - [c4]Edoardo Fusella, José Flich, Alessandro Cilardo, Antonino Mazzeo:
On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs. SiPhotonics@HiPEAC 2015: 9-16 - [c3]Edoardo Fusella, Alessandro Cilardo:
Crosstalk-Aware Mapping for Tile-Based Optical Network-on-Chip. HPCC/CSS/ICESS 2015: 1139-1142 - 2014
- [j1]Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca:
Automated design space exploration for FPGA-based heterogeneous interconnects. Des. Autom. Embed. Syst. 18(3-4): 157-170 (2014) - [c2]Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo:
Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems. DATE 2014: 1-4 - 2013
- [c1]Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo:
Automated synthesis of FPGA-based heterogeneous interconnect topologies. FPL 2013: 1-8
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