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ORCIDRenato Stefanelli
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2010 – 2019
- 2011
[j18]Marco D. Santambrogio
, Renato Stefanelli:
A New Compact SD2 Positive Integer Triangular Array Division Circuit. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 42-51 (2011)
2000 – 2009
- 2002
- [c20]Fabio Salice, Mariagiovanna Sami, Renato Stefanelli:
Fault-Tolerant CAM Architectures: A Design Framework. DFT 2002: 233-244
1990 – 1999
- 1998
- [c19]Donatella Sciuto, Cristina Silvano, Renato Stefanelli:
Systematic AUED Codes for Self-Checking Architectures. DFT 1998: 183-191 - 1997
- [c18]Cristiana Bolchini, Giacomo Buonanno, M. Cozzini, Donatella Sciuto, Renato Stefanelli:
Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks. DFT 1997: 204-211 - [c17]Fausto Distante, Mariagiovanna Sami, Renato Stefanelli:
Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance. DFT 1997: 261-271 - [c16]Fausto Distante, Mariagiovanna Sami, Renato Stefanelli:
Array partitioning to achieve defect tolerance. EUROMICRO 1997: 487-491 - 1996
- [c15]Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
Fault detection and fault tolerance issues at CMOS level through AUED encoding. DFT 1996: 258-267 - [c14]Giovanni A. Mojoli, Davide Salvi, M. G. Sami, Giacomo R. Sechi, Renato Stefanelli:
KITE: a behavioural approach to fault-tolerance in FPGA-based systems. DFT 1996: 327-334 - 1995
- [c13]Mariagiovanna Sami, Fausto Distante, Renato Stefanelli:
A Channel-Constrained Reconfiguration Approach for Processing Arrays. DFT 1995: 99-107 - [c12]Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
A new switching-level approach to multiple-output functions synthesis. VLSI Design 1995: 125-129 - 1994
- [j17]Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
Innovative Structures for CMOS Combinational Gates Synthesis. IEEE Trans. Computers 43(4): 385-399 (1994) - [c11]Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
A CMOS Fault Tolerant Architecture for Swith-Level Faults. DFT 1994: 10-18 - [c10]Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
CMOS Reliability Improvements Through a New Fault Tolerant Technique. ISCAS 1994: 83-86 - 1993
- [j16]M. G. Sami, Donatella Sciuto, Renato Stefanelli:
Concurrently self-checking structures for Fsms. Microprocess. Microprogramming 39(2-5): 237-240 (1993) - [c9]Luigi Dadda, Vincenzo Piuri, Renato Stefanelli:
Multi-parallel convolvers. IEEE Symposium on Computer Arithmetic 1993: 70-77 - [c8]A. Dell'Acqua, M. Hansen, Sami J. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, Aurore Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, Simona Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson:
System Level Policies for Fault Tolerance Issues in the FERMI Project. DFT 1993: 1-8 - [c7]Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
New CMOS Structures for the Synthesis of Dominant Functions. VLSI Design 1993: 367-370 - [e2]Fabrizio Lombardi, Mariagiovanna Sami, Yvon Savaria, Renato Stefanelli:
The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 27-29, 1993, Venice, Italy, Proceedings. IEEE Computer Society 1993, ISBN 0-8186-3502-9 [contents] - 1992
- [j15]Vincenzo Piuri, Renato Stefanelli:
Fault-tolerant techniques for VLSI tree structures. Microprocess. Microprogramming 34(1-5): 97-102 (1992) - [j14]Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto, Renato Stefanelli:
A behavioral approach to testability analysis for neural networks. Microprocess. Microprogramming 35(1-5): 181-186 (1992) - 1991
- [j13]Vincenzo Piuri, Renato Stefanelli:
Concurrent error detection in parallel multipliers and complex arithmetic structures: Remarks on the use of the 3n code. Microprocessing and Microprogramming 31(1-5): 47-52 (1991) - [j12]Fausto Distante, Mariagiovanna Sami, Renato Stefanelli, Giancarlo Storti-Gajan:
Mapping neural nets onto a massively parallel architecture: a defect-tolerance solution. Proc. IEEE 79(4): 444-460 (1991) - [j11]Virginio Cantoni, V. Gesu, Marco Ferretti, Stefano Levialdi, Roberto M. Negrini, Renato Stefanelli:
The PAPIA system. J. VLSI Signal Process. 2(4): 195-217 (1991) - [c6]Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
Optimization techniques for multiple output function synthesis. EURO-DAC 1991: 545-551 - 1990
- [j10]Fausto Distante, M. G. Sami, Renato Stefanelli, Giancarlo Storti Gajani:
Area compaction in silicon structures for neural net implementation. Microprocessing and Microprogramming 28(1-5): 139-143 (1990)
1980 – 1989
- 1989
- [b1]Roberto M. Negrini, Mariagiovanna Sami, Renato Stefanelli:
Fault-tolerance through reconfiguration of VLSI and WSI awards. MIT Press series in computer systems, MIT Press 1989, ISBN 978-0-262-14044-7, pp. 1-301 - [j9]Fabrizio Lombardi, Mariagiovanna Sami, Renato Stefanelli:
Reconfiguration of VLSI arrays by covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(9): 952-965 (1989) - 1988
- [j8]Vincenzo Piuri, Renato Stefanelli, Giovanni Traverso:
Error detection in serial multipliers and in systolic arrays: An approach based upon A★N codes. Microprocess. Microprogramming 23(1-5): 63-73 (1988) - [j7]Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli:
An algorithm for functional reconfiguration of fixed-size arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(10): 1114-1118 (1988) - [c5]Vincenzo Piuri, Renato Stefanelli:
Use of redundant binary representation for fault-tolerant arithmetic array processors. ICCD 1988: 496-501 - 1987
- [c4]Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli:
A Technique for Reconfiguring Two Dimensional VLSI Arrays. RTSS 1987: 44-53 - [e1]Mary Jane Irwin, Renato Stefanelli:
8th IEEE Symposium on Computer Arithmetic, ARITH 1987, Como, Italy, May 18-21, 1987. IEEE Computer Society 1987, ISBN 0-8186-0774-2 [contents] - 1986
- [j6]Roberto M. Negrini, Mariagiovanna Sami, Renato Stefanelli:
Fault Tolerance Fechniques for Array Structures Used in Supercomputing. Computer 19(2): 78-87 (1986) - [j5]Mariagiovanna Sami, Renato Stefanelli:
Reconfigurable architectures for VLSI processing arrays. Proc. IEEE 74(5): 712-722 (1986) - [j4]Renato Stefanelli:
A comment on an investigation into the skeletonization approach of Hilditch. Pattern Recognit. 19(1): 13-14 (1986) - 1985
- [c3]Virginio Cantoni, Marco Ferretti, Stefano Levialdi, Renato Stefanelli:
PAPIA: Pyramidal architecture for parallel image analysis. IEEE Symposium on Computer Arithmetic 1985: 237-242 - 1983
- [c2]Mariagiovanna Sami, Renato Stefanelli:
Reconfigurable architectures for VLSI processing arrays. AFIPS National Computer Conference 1983: 565-577 - [c1]Marco Annaratone, Renato Stefanelli:
A multiplier with multiple error correction capability. IEEE Symposium on Computer Arithmetic 1983: 44-51
1970 – 1979
- 1973
- [j3]Mariagiovanna Sami, Renato Stefanelli:
Compression algorithms that preserve basic topological features in binary-coded patterns. Pattern Recognit. 5(2): 133-147 (1973) - 1972
- [j2]Renato Stefanelli:
A Suggestion for a High-Speed Parallel Binary Divider. IEEE Trans. Computers 21(1): 42-55 (1972) - 1971
- [j1]Renato Stefanelli, Azriel Rosenfeld:
Some Parallel Thinning Algorithms for Digital Pictures. J. ACM 18(2): 255-264 (1971)
Coauthor Index
aka: M. G. Sami
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