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ORCIDSherief Reda
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Publications
- 2019
[j23]Kumud Nepal, Soheil Hashemi
, Hokchhay Tann, R. Iris Bahar, Sherief Reda:
Automated High-Level Generation of Low-Power Approximate Computing Circuits. IEEE Trans. Emerg. Top. Comput. 7(1): 18-30 (2019)- 2017
- [c70]Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda:
Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. DAC 2017: 28:1-28:6 - [c69]Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda:
Understanding the impact of precision quantization on the accuracy and energy of neural networks. DATE 2017: 1474-1479 - [i3]Hokchhay Tann, Soheil Hashemi, Iris Bahar, Sherief Reda:
Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. CoRR abs/1705.04288 (2017) - 2016
- [c62]Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda:
Runtime configurable deep neural networks for energy-accuracy trade-off. CODES+ISSS 2016: 34:1-34:10 - [c61]Soheil Hashemi, R. Iris Bahar, Sherief Reda:
A low-power dynamic divider for approximate applications. DAC 2016: 105:1-105:6 - [c59]Onur Ulusel, Christopher B. Picardo, Christopher B. Harris, Sherief Reda, R. Iris Bahar:
Hardware acceleration of feature detection and description algorithms on low-power embedded platforms. FPL 2016: 1-9 - [i2]Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda:
Runtime Configurable Deep Neural Networks for Energy-Accuracy Trade-off. CoRR abs/1607.05418 (2016) - [i1]Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda:
Understanding the Impact of Precision Quantization on the Accuracy and Energy of Neural Networks. CoRR abs/1612.03940 (2016) - 2015
- [c56]Soheil Hashemi, R. Iris Bahar, Sherief Reda:
DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications. ICCAD 2015: 418-425 - 2014
- [j17]Onur Ulusel, Kumud Nepal, R. Iris Bahar, Sherief Reda:
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators. ACM Trans. Reconfigurable Technol. Syst. 7(1): 4:1-4:22 (2014) - [c53]Kumud Nepal, Yueting Li, R. Iris Bahar, Sherief Reda:
ABACUS: A technique for automated behavioral synthesis of approximate computing circuits. DATE 2014: 1-6 - 2012
- [c45]Kumud Nepal, Onur Ulusel, R. Iris Bahar, Sherief Reda:
Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. FCCM 2012: 65-68 - 2009
- [c32]Roto Le, Sherief Reda, R. Iris Bahar:
High-performance, cost-effective heterogeneous 3D FPGA architectures. FPGA 2009: 286 - [c30]Roto Le, Sherief Reda, R. Iris Bahar:
High-performance, cost-effective heterogeneous 3D FPGA architectures. ACM Great Lakes Symposium on VLSI 2009: 251-256 - [c29]Sherief Reda, Aung Si, R. Iris Bahar:
Reducing the leakage and timing variability of 2D ICcs using 3D ICs. ISLPED 2009: 283-286 - 2008
- [j8]Cesare Ferri, Sherief Reda, R. Iris Bahar:
Parametric yield management for 3D ICs: Models and strategies for improvement. ACM J. Emerg. Technol. Comput. Syst. 4(4): 19:1-19:22 (2008) - 2007
- [c24]Cesare Ferri, Sherief Reda, R. Iris Bahar:
Strategies for improving the parametric yield and profits of 3D ICs. ICCAD 2007: 220-226
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