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2020 – today
- 2024
[j17]Ryoki Hamano
, Shota Saito, Masahiro Nomura, Shinichi Shirakawa:
Marginal Probability-Based Integer Handling for CMA-ES Tackling Single- and Multi-Objective Mixed-Integer Black-Box Optimization. ACM Trans. Evol. Learn. Optim. 4(2): 10 (2024)- [c35]Ryoki Hamano, Shota Saito, Masahiro Nomura, Kento Uchida, Shinichi Shirakawa:
CatCMA : Stochastic Optimization for Mixed-Category Problems. GECCO 2024 - [c34]Shion Takeno, Masahiro Nomura, Masayuki Karasuyama:
Hot off the Press: Towards Practical Preferential Bayesian Optimization with Skew Gaussian Processes. GECCO Companion 2024: 59-60 - [c33]Kento Uchida, Ryoki Hamano, Masahiro Nomura, Shota Saito, Shinichi Shirakawa:
CMA-ES for Safe Optimization. GECCO 2024 - [c32]Yuta Saito, Masahiro Nomura:
Hyperparameter Optimization Can Even Be Harmful in Off-Policy Learning and How to Deal with It. IJCAI 2024: 4860-4867 - [c31]Kento Uchida, Ryoki Hamano, Masahiro Nomura, Shota Saito, Shinichi Shirakawa:
CMA-ES for Discrete and Mixed-Variable Optimization on Sets of Points. PPSN (2) 2024: 236-251 - [c30]Ryoki Hamano, Shinichi Shirakawa, Masahiro Nomura:
Natural Gradient Interpretation of Rank-One Update in CMA-ES. PPSN (2) 2024: 252-267 - [c29]Tatsuhiro Shimizu, Koichi Tanaka, Ren Kishimoto, Haruka Kiyohara, Masahiro Nomura, Yuta Saito:
Effective Off-Policy Evaluation and Learning in Contextual Combinatorial Bandits. RecSys 2024: 733-741 - [c28]Haruka Kiyohara, Masahiro Nomura, Yuta Saito:
Off-Policy Evaluation of Slate Bandit Policies via Optimizing Abstraction. WWW 2024: 3150-3161 - [i23]Masahiro Nomura, Youhei Akimoto, Isao Ono:
CMA-ES with Learning Rate Adaptation. CoRR abs/2401.15876 (2024) - [i22]Masahiro Nomura, Masashi Shibata:
cmaes : A Simple yet Practical Python Library for CMA-ES. CoRR abs/2402.01373 (2024) - [i21]Haruka Kiyohara, Masahiro Nomura, Yuta Saito:
Off-Policy Evaluation of Slate Bandit Policies via Optimizing Abstraction. CoRR abs/2402.02171 (2024) - [i20]Yuta Saito, Masahiro Nomura:
Hyperparameter Optimization Can Even be Harmful in Off-Policy Learning and How to Deal with It. CoRR abs/2404.15084 (2024) - [i19]Ryoki Hamano, Shota Saito, Masahiro Nomura, Kento Uchida, Shinichi Shirakawa:
CatCMA : Stochastic Optimization for Mixed-Category Problems. CoRR abs/2405.09962 (2024) - [i18]Kento Uchida, Ryoki Hamano, Masahiro Nomura, Shota Saito, Shinichi Shirakawa:
CMA-ES for Safe Optimization. CoRR abs/2405.10534 (2024) - [i17]Ryoki Hamano, Shinichi Shirakawa, Masahiro Nomura:
Natural Gradient Interpretation of Rank-One Update in CMA-ES. CoRR abs/2406.16506 (2024) - [i16]Tatsuhiro Shimizu, Koichi Tanaka, Ren Kishimoto, Haruka Kiyohara, Masahiro Nomura, Yuta Saito:
Effective Off-Policy Evaluation and Learning in Contextual Combinatorial Bandits. CoRR abs/2408.11202 (2024) - [i15]Kento Uchida, Ryoki Hamano, Masahiro Nomura, Shota Saito, Shinichi Shirakawa:
CMA-ES for Discrete and Mixed-Variable Optimization on Sets of Points. CoRR abs/2408.13046 (2024) - [i14]Kento Masui, Mayu Otani, Masahiro Nomura, Hideki Nakayama:
Harnessing the Latent Diffusion Model for Training-Free Image Style Transfer. CoRR abs/2410.01366 (2024) - 2023
- [c27]Masahiro Nomura, Youhei Akimoto, Isao Ono:
CMA-ES with Learning Rate Adaptation: Can CMA-ES with Default Population Size Solve Multimodal and Noisy Problems? GECCO 2023: 839-847 - [c26]Yohei Watanabe, Kento Uchida, Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa:
(1+1)-CMA-ES with Margin for Discrete and Mixed-Integer Problems. GECCO 2023: 882-890 - [c25]Shion Takeno, Masahiro Nomura, Masayuki Karasuyama:
Towards Practical Preferential Bayesian Optimization with Skew Gaussian Processes. ICML 2023: 33516-33533 - [i13]Shion Takeno, Masahiro Nomura, Masayuki Karasuyama:
Towards Practical Preferential Bayesian Optimization with Skew Gaussian Processes. CoRR abs/2302.01513 (2023) - [i12]Masahiro Nomura, Youhei Akimoto, Isao Ono:
CMA-ES with Learning Rate Adaptation: Can CMA-ES with Default Population Size Solve Multimodal and Noisy Problems? CoRR abs/2304.03473 (2023) - [i11]Yohei Watanabe, Kento Uchida, Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa:
(1+1)-CMA-ES with Margin for Discrete and Mixed-Integer Problems. CoRR abs/2305.00849 (2023) - 2022
- [j16]Yoshihiko Ozaki, Yuki Tanigaki, Shuhei Watanabe, Masahiro Nomura, Masaki Onishi:
Multiobjective Tree-Structured Parzen Estimator. J. Artif. Intell. Res. 73: 1209-1250 (2022) - [c24]Masahiro Nomura, Isao Ono:
Fast Moving Natural Evolution Strategy for High-Dimensional Problems. CEC 2022: 1-8 - [c23]Masahiro Nomura, Isao Ono:
Towards a Principled Learning Rate Adaptation for Natural Evolution Strategies. EvoApplications 2022: 721-737 - [c22]Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa:
CMA-ES with margin: lower-bounding marginal probability for mixed-integer black-box optimization. GECCO 2022: 639-647 - [c21]Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa:
Benchmarking CMA-ES with margin on the bbob-mixint testbed. GECCO Companion 2022: 1708-1716 - [c20]Yuta Saito, Masahiro Nomura:
Towards Resolving Propensity Contradiction in Offline Recommender Learning. IJCAI 2022: 2211-2217 - [i10]Masahiro Kato, Kaito Ariu, Masaaki Imaizumi, Masatoshi Uehara, Masahiro Nomura, Chao Qin:
Optimal Fixed-Budget Best Arm Identification using the Augmented Inverse Probability Weighting Estimator in Two-Armed Gaussian Bandits with Unknown Variances. CoRR abs/2201.04469 (2022) - [i9]Masahiro Nomura, Isao Ono:
Fast Moving Natural Evolution Strategy for High-Dimensional Problems. CoRR abs/2201.11422 (2022) - [i8]Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa:
CMA-ES with Margin: Lower-Bounding Marginal Probability for Mixed-Integer Black-Box Optimization. CoRR abs/2205.13482 (2022) - [i7]Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa:
CMA-ES with Margin for Single-and Multi-Objective Mixed-Integer Black-Box Optimization. CoRR abs/2212.09260 (2022) - 2021
- [c19]Masahiro Nomura, Shuhei Watanabe, Youhei Akimoto, Yoshihiko Ozaki, Masaki Onishi:
Warm Starting CMA-ES for Hyperparameter Optimization. AAAI 2021: 9188-9196 - [c18]Masahiro Nomura, Nobuyuki Sakai, Nobusumi Fukushima, Isao Ono:
Distance-weighted Exponential Natural Evolution Strategy for Implicitly Constrained Black-Box Function Optimization. CEC 2021: 1099-1106 - [c17]Masahiro Nomura, Yuta Saito:
Efficient Hyperparameter Optimization under Multi-Source Covariate Shift. CIKM 2021: 1376-1385 - [c16]Masahiro Nomura, Isao Ono:
Natural Evolution Strategy for Unconstrained and Implicitly Constrained Problems with Ridge Structure. SSCI 2021: 1-7 - [i6]Masahiro Nomura, Isao Ono:
Natural Evolution Strategy for Unconstrained and Implicitly Constrained Problems with Ridge Structure. CoRR abs/2108.09455 (2021) - [i5]Masahiro Nomura, Isao Ono:
Towards a Principled Learning Rate Adaptation for Natural Evolution Strategies. CoRR abs/2112.10680 (2021) - 2020
- [c15]Shintaro Takenaga, Shuhei Watanabe, Masahiro Nomura, Yoshihiko Ozaki, Masaki Onishi, Hitoshi Habe:
Evaluating Initialization of Nelder-Mead Method for Hyperparameter Optimization in Deep Learning. ICPR 2020: 3372-3379 - [i4]Masahiro Nomura, Yuta Saito:
Multi-Source Unsupervised Hyperparameter Optimization. CoRR abs/2006.10600 (2020) - [i3]Masahiro Nomura:
Simple and Scalable Parallelized Bayesian Optimization. CoRR abs/2006.13600 (2020) - [i2]Masahiro Nomura, Shuhei Watanabe, Youhei Akimoto, Yoshihiko Ozaki, Masaki Onishi:
Warm Starting CMA-ES for Hyperparameter Optimization. CoRR abs/2012.06932 (2020)
2010 – 2019
- 2019
- [j15]Masahiro Nomura, Katsuhiro Nakamura:
On Fail-Stop Signature Schemes with H-EUC Security. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(1): 125-147 (2019) - [c14]Masahiro Nomura:
Heat Transfer in Nanostructured Si and Heat Flux Control Technique. 3DIC 2019: 1-4 - [i1]Masahiro Nomura, Kenshi Abe:
A Simple Heuristic for Bayesian Optimization with A Low Budget. CoRR abs/1911.07790 (2019) - 2014
- [j14]Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. IEEE J. Solid State Circuits 49(2): 536-544 (2014) - 2013
- [j13]Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits. IEEE J. Solid State Circuits 48(8): 1986-1994 (2013) - [j12]Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1175-1179 (2013) - [c13]Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Variation-aware subthreshold logic circuit design. ASICON 2013: 1-4 - [c12]Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits. ISSCC 2013: 436-437 - 2012
- [j11]Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno:
A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. IEEE J. Solid State Circuits 47(4): 832-840 (2012) - [j10]Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 918-921 (2012) - [c11]Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. CICC 2012: 1-4 - [c10]Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai:
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits. ISQED 2012: 586-591 - [c9]Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. ISSCC 2012: 486-488 - 2011
- [j9]Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi:
Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs. IEEE J. Solid State Circuits 46(4): 806-814 (2011) - [j8]Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits. IEEE Trans. Circuits Syst. II Express Briefs 58-II(5): 294-298 (2011) - [c8]Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates. DAC 2011: 984-989 - [c7]Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai:
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. ESSCIRC 2011: 191-194 - [c6]Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. ISLPED 2011: 21-26 - [c5]Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics. ISLPED 2011: 163-168 - [c4]Kentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Reduction of minimum operating voltage (VDDmin) of CMOS logic circuits with post-fabrication automatically selective charge injection. ISLPED 2011: 175-180 - 2010
- [c3]Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai:
Misleading energy and performance claims in sub/near threshold digital systems. ICCAD 2010: 625-631
2000 – 2009
- 2008
- [j7]Yoshifumi Ikenaga, Masahiro Nomura, Yoetsu Nakazawa, Yasuhiko Hagihara:
A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations. IEEE J. Solid State Circuits 43(4): 911-918 (2008) - 2006
- [j6]Masahiro Nomura, Taku Ohsawa, Koichi Takeda, Yoetsu Nakazawa, Yoshinori Hirota, Yasuhiko Hagihara, Naoki Nishi:
An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques. IEICE Trans. Electron. 89-C(3): 334-341 (2006) - [j5]Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, Yoetsu Nakazawa, Toshio Ishii, Hiroyuki Kobatake:
A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. IEEE J. Solid State Circuits 41(1): 113-121 (2006) - [j4]Masahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda, Yoetsu Nakazawa, Yoshiharu Aimoto, Yasuhiko Hagihara:
Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes. IEEE J. Solid State Circuits 41(4): 805-814 (2006) - [c2]Koichi Takeda, Hidetoshi Ikeda, Yasuhiko Hagihara, Masahiro Nomura, Hiroyuki Kobatake:
Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit. ISSCC 2006: 2602-2611
1990 – 1999
- 1999
- [j3]Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina:
A 2000-MOPS embedded RISC processor with a Rambus DRAM controller. IEEE J. Solid State Circuits 34(7): 1010-1021 (1999) - 1994
- [j2]Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada:
A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. IEEE J. Solid State Circuits 29(3): 290-297 (1994) - [j1]Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youich Yano, Hachiro Yamada:
A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor. IEEE J. Solid State Circuits 29(12): 1464-1473 (1994) - 1990
- [c1]Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi:
Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. ISMVL 1990: 355-362
Coauthor Index
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