Philippe Vialletelle

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Stéphane Dauzère-Pérès

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Publications

2023
[j5]
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Melek Rodoplu, Stéphane Dauzère-Pérès, Philippe Vialletelle:
Integrated planning of maintenance operations and workload allocation. Int. J. Prod. Res. 61(23): 8291-8308 (2023)
2022
[j4]
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  - journals/cor/PerraudatDV22
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Antoine Perraudat, Stéphane Dauzère-Pérès, Philippe Vialletelle:
Optimizing multiple qualifications of products on non-identical parallel machines. Comput. Oper. Res. 144: 105813 (2022)
2021
[j3]
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  - journals/ijpr/LimaBDV21
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Alexandre Lima, Valeria Borodin, Stéphane Dauzère-Pérès, Philippe Vialletelle:
A sampling-based approach for managing lot release in time constraint tunnels in semiconductor manufacturing. Int. J. Prod. Res. 59(3): 860-884 (2021)
2020
[c14]
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  - conf/wsc/LendermannDMMOS20
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Peter Lendermann, Stéphane Dauzère-Pérès, Leon F. McGinnis, Lars Mönch, Tina O'Donnell, Georg Seidel, Philippe Vialletelle:
Scheduling and Simulation in wafer fabs: Competitors, Independent Players or Amplifiers? WSC 2020: 1861-1874
[c13]
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  - conf/wsc/MoritzDAV20
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Alexandre Moritz, Stéphane Dauzère-Pérès, Oussama Ben-Ammar, Philippe Vialletelle:
Maintenance with Production Planning Constraints in Semiconductor Manufacturing. WSC 2020: 1921-1930
2019
[j2]
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  - journals/cii/LimaBDV19
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Alexandre Lima, Valeria Borodin, Stéphane Dauzère-Pérès, Philippe Vialletelle:
Sampling-based release control of multiple lots in time constraint tunnels. Comput. Ind. 110: 3-11 (2019)
[c12]
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  - conf/wsc/PerraudatDV19
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Antoine Perraudat, Stéphane Dauzère-Pérès, Philippe Vialletelle:
Evaluating the Impact of Dynamic Qualification Management in Semiconductor Manufacturing. WSC 2019: 2336-2347
2018
[c11]
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  - conf/wsc/LaippleDPV18
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Georg Laipple, Stéphane Dauzère-Pérès, Thomas Ponsignon, Philippe Vialletelle:
Generic Data Model for semiconductor manufacturing supply Chains. WSC 2018: 3615-3626
2017
[c10]
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  - conf/wsc/LimaBDV17
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Alexandre Lima, Valeria Borodin, Stéphane Dauzère-Pérès, Philippe Vialletelle:
Analyzing different dispatching policies for probability estimation in time constraint tunnels in semiconductor manufacturing. WSC 2017: 3543-3554
2016
[c8]
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  - conf/wsc/PianneRDV16
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Amelie Pianne, Luis Rivero, Stéphane Dauzère-Pérès, Philippe Vialletelle:
Ideal and potential flexibility measures for qualification management in semiconductor manufacturing. WSC 2016: 2621-2632
2014
[c7]
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  - conf/case/YugmaBDV14
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Claude Yugma, Jakey Blue, Stéphane Dauzère-Pérès, Philippe Vialletelle:
Integration of scheduling and advanced process control in semiconductor manufacturing: review and outlook. CASE 2014: 93-98
2013
[c5]
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  - conf/wsc/AmiraLVDYL13
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Ahmed Ben Amira, Guillaume Lepelletier, Philippe Vialletelle, Stéphane Dauzère-Pérès, Claude Yugma, Philippe Lalevée:
Modeling complex processability constraints in high-mix semiconductor manufacturing. WSC 2013: 3719-3730
2012
[c4]
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  - conf/wsc/MungaDVY12
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Justin Nduhura Munga, Stéphane Dauzère-Pérès, Philippe Vialletelle, Claude Yugma:
Industrial implementation of a dynamic sampling algorithm in semiconductor manufacturing: approach and challenges. WSC 2012: 192:1-192:9
2011
[c3]
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  - conf/wsc/YugmaDRVPR11
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Claude Yugma, Stéphane Dauzère-Pérès, Jean-Loup Rouveyrol, Philippe Vialletelle, Jacques Pinaton, Christophe Relliaud:
A smart sampling scheduling and skipping simulator and its evaluation on real data sets. WSC 2011: 1908-1917
[c2]
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  - conf/wsc/MungaVDY11
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Justin Nduhura Munga, Philippe Vialletelle, Stéphane Dauzère-Pérès, Claude Yugma:
Optimized management of excursions in semiconductor manufacturing. WSC 2011: 2105-2112
2008
[c1]
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  - conf/wsc/JohnzenVDYD08
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Carl Johnzen, Philippe Vialletelle, Stéphane Dauzère-Pérès, Claude Yugma, Alexandre Derreumaux:
Impact of qualification management on scheduling in semiconductor manufacturing. WSC 2008: 2059-2066

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