A Business-to-Business Collaboration System That Promotes Data Utilization While Encrypting Information on the Blockchain - Hiroaki Nasu; Yuta Kodera; Yasuyuki Nogami (Sensors, 2022)

Secure Comparison Protocol for Promoting Business to Business Collaboration on the Blockchain - Hiroaki Nasu; Yuta Kodera; Yasuyuki Nogami (IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021, Penghu, Taiwan, September 15-17, 2021, 2021)

A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology - Noboru Shibata; Takahisa Kawabe; Taira Shibuya; Mario Sako; Kosuke Yanagidaira; Toshifumi Hashimoto; Hiroki Date; Manabu Sato; Tomoki Nakagawa; Junji Musha; Takatoshi Minamoto; Kazushige Kanda; et al. (IEEE J. Solid State Circuits, 2020)

A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology - Noboru Shibata; Kazushige Kanda; Takahiro Shimizu; Jun Nakai; Osamu Nagao; Naoki Kobayashi; Makoto Miakashi; Yasushi Nagadomi; Takeshi Nakano; Takahisa Kawabe; Taira Shibuya; Mario Sako; et al. (IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019, 2019)

A 19nm 112.8mm\(^2\) 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface - Noboru Shibata; Kazushige Kanda; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yui Shimizu; Takahiro Shimizu; Takahiro Sugimoto; Tomohiro Kobayashi; Kazuko Inuzuka; Naoaki Kanagawa; Yasuyuki Kajitani; et al. (2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012, 2012)

A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology - Raul Cernea; Long Pham; Farookh Moogat; Siu Lung Chan; Binh Le; Yan Li; Shouchang Tsao; Taiyuan Tseng; Khanh Nguyen; Jason Li; Jayson Hu; Jonghak Yuh; et al. (IEEE J. Solid State Circuits, 2009)

A 113mm2 32Gb 3b/cell NAND flash memory - Takuya Futatsuyama; Norihiro Fujita; Naoya Tokiwa; Yoshihiko Shindo; Toshiaki Edahiro; Teruhiko Kamei; Hiroaki Nasu; Makoto Iwai; Koji Kato; Yasuyuki Fukuda; Naoaki Kanagawa; Naofumi Abiko; et al. (IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009, 2009)

A Method for Constructing a Pseudo Self-Dual Normal Basis - Hiroaki Nasu; Yasuyuki Nogami; Satoshi Uehara; Ryo Namba; Yoshitaka Morikawa (Cybern. Syst., 2008)

A method for constructing a self-dual normal basis in odd characteristic extension fields - Yasuyuki Nogami; Hiroaki Nasu; Yoshitaka Morikawa; Satoshi Uehara (Finite Fields Their Appl., 2008)

A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm - Raul Cernea; Long Pham; Farookh Moogat; Siu Lung Chan; Binh Le; Yan Li; Shouchang Tsao; Taiyuan Tseng; Khanh Nguyen; Jason Li; Jayson Hu; Jong Park; et al. (2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008, 2008)

A 146-mm\(^2\) 8-gb multi-level NAND flash memory with 70-nm CMOS technology - Takahiko Hara; Koichi Fukuda; Kazuhisa Kanazawa; Noboru Shibata; Koji Hosono; Hiroshi Maejima; Michio Nakagawa; Takumi Abe; Masatsugu Kojima; Masaki Fujiu; Yoshiaki Takeuchi; Kazumi Amemiya; et al. (IEEE J. Solid State Circuits, 2006)