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ORCIDTakeshi Matsumoto
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2020 – today
- 2024
[j11]Yuki Uehara, Naoki Nishimura, Yilin Li, Jie Yang, Deddy Jobson, Koya Ohashi, Takeshi Matsumoto, Noriyoshi Sukegawa
, Yuichi Takano:
Robust portfolio optimization model for electronic coupon allocation. INFOR Inf. Syst. Oper. Res. 62(4): 646-660 (2024)- [c34]Deddy Jobson, Yilin Li, Naoki Nishimura, Koya Ohashi, Jie Yang, Takeshi Matsumoto:
Covariate Ordered Systematic Sampling as an Improvement to Randomized Controlled Trials. CIKM 2024: 3812-3816 - [c33]Yuki Uehara, Shunnosuke Ikeda, Naoki Nishimura, Koya Ohashi, Yilin Li, Jie Yang, Deddy Jobson, Xingxia Zha, Takeshi Matsumoto, Noriyoshi Sukegawa, Yuichi Takano:
Fast Solution to the Fair Ranking Problem Using the Sinkhorn Algorithm. PRICAI (5) 2024: 207-215 - [i2]Yuki Uehara, Naoki Nishimura, Yilin Li, Jie Yang, Deddy Jobson, Koya Ohashi, Takeshi Matsumoto, Noriyoshi Sukegawa, Yuichi Takano:
Robust portfolio optimization model for electronic coupon allocation. CoRR abs/2405.12865 (2024) - [i1]Yuki Uehara, Shunnosuke Ikeda, Naoki Nishimura, Koya Ohashi, Yilin Li, Jie Yang, Deddy Jobson, Xingxia Zha, Takeshi Matsumoto, Noriyoshi Sukegawa, Yuichi Takano:
Fast solution to the fair ranking problem using the Sinkhorn algorithm. CoRR abs/2406.10262 (2024)
2010 – 2019
- 2019
- [c32]Qinhao Wang, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
High-Level Engineering Change Through Programmable Datapath and SMT Solvers. ISCAS 2019: 1-5 - 2018
- [c31]Ryotaro Konoike, Keijiro Suzuki, Takashi Inoue, Takeshi Matsumoto, Teruo Kurahashi, Ayahito Uetake, Kazumasa Takabayashi, Suguru Akiyama, Shigeaki Sekiguchi, Kazuhiro Ikeda, Shu Namiki, Hitoshi Kawashima:
Lossless Operation of SOA-Integrated Silicon Photonics Switch for 8 × 32-Gbaud 16-QAM WDM Signals. OFC 2018: 1-3 - [c30]Takeshi Matsumoto, Teruo Kurahashi, Ryotaro Konoike, Ken Tanizawa, Keijiro Suzuki, Ayahito Uetake, Kazumasa Takabayashi, Kazuhiro Ikeda, Hitoshi Kawashima, Suguru Akiyama, Shigeaki Sekiguchi:
In-line Optical Amplification for Silicon Photonics Platform by Flip-Chip Bonded InP-SOAs. OFC 2018: 1-3 - 2017
- [j10]Ryosuke Higashi, Toshihiro Sera, Hisashi Naito, Takeshi Matsumoto, Masao Tanaka:
Pulmonary kinematic analysis with non-rigid deformable registration for detecting localised emphysema. Comput. methods Biomech. Biomed. Eng. Imaging Vis. 5(2): 100-109 (2017) - [j9]Hideki Toda, Takeshi Matsumoto, Takeuchi Hiroya:
Experimental Study of Ankle Joint Pushing Mechanism Concerning About the Horizontal Movement of Talus. J. Robotics Mechatronics 29(2): 299-305 (2017) - [j8]Takeshi Matsumoto, Daichi Goto:
Effect of low-intensity whole-body vibration on bone defect repair and associated vascularization in mice. Medical Biol. Eng. Comput. 55(12): 2257-2266 (2017) - [c29]Yuichi Kobayashi, Takeshi Matsumoto, Wataru Takano, Dirk Wollherr, Volker Gabler:
Motion recognition by natural language including success and failure of tasks for co-working robot with human. AIM 2017: 10-15 - 2016
- [c28]Takeshi Matsumoto, Teruo Kurahashi, Ken Tanizawa, Keijiro Suzuki, Ayahito Uetake, Kazumasa Takabayashi, Kazuhiro Ikeda, Hitoshi Kawashima, Suguru Akiyama:
In-line optical amplification for Si waveguides on 1×8 splitter and selector by flip-chip bonded InP-SOAs. OFC 2016: 1-3 - 2015
- [c27]Takeuchi Hiroya, Hideki Toda, Takeshi Matsumoto:
Proposal of an ankle joint bending machine using exoskeleton support from foot to hip. ROBIO 2015: 799-801 - [c26]Shridhar Choudhary, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
Trace signal selection methods for post silicon debugging. VLSI-SoC 2015: 258-263 - 2014
- [j7]Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita:
SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions. IPSJ Trans. Syst. LSI Des. Methodol. 7: 46-55 (2014) - [c25]S. Tanaka, Takeshi Matsumoto, Teruo Kurahashi, M. Matsuda, Ayahito Uetake, S. Sekiguchi, Y. Tanaka, K. Morito:
Flip-chip-bonded, 8-wavelength AlGaInAs DFB laser array operable up to 70°C for silicon WDM interconnects. ECOC 2014: 1-3 - 2013
- [c24]Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
Rectification of advanced microprocessors without changing routing on FPGAs (abstract only). FPGA 2013: 279 - [c23]Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
Debugging processors with advanced features by reprogramming LUTs on FPGA. FPT 2013: 50-57 - [c22]Will X. Y. Li, Shridhar Chaudhary, Ray C. C. Cheung, Takeshi Matsumoto, Masahiro Fujita:
Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computing. FPT 2013: 478-479 - [c21]Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita:
Hardware implementation of BLTL property checkers for acceleration of statistical model checking. ICCAD 2013: 670-676 - [c20]Masahiro Fujita, Satoshi Jo, Shohei Ono, Takeshi Matsumoto:
Partial synthesis through sampling with and without specification. ICCAD 2013: 787-794 - [c19]Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita:
Debugging Methods Through Identification of Appropriate Functions for Internal Gates. VLSI-SoC (Selected Papers) 2013: 1-22 - [c18]Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita:
A debugging method for gate level circuit designs by introducing programmability. VLSI-SoC 2013: 78-83 - [c17]Masahiro Fujita, Takeshi Matsumoto, Satoshi Jo:
FOF: Functionally Observable Fault and its ATPG techniques. VLSI-SoC 2013: 108-111 - 2012
- [c16]Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita:
SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions. Asian Test Symposium 2012: 19-24 - [c15]Shohei Ono, Takeshi Matsumoto, Masahiro Fujita:
Automatic assertion extraction in gate-level simulation using GPGPUs. ICCD 2012: 522-523 - [c14]Takeshi Matsumoto, Shohei Ono, Masahiro Fujita:
An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence. VLSI-SoC 2012: 291-294 - 2011
- [j6]Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
Multi-Level Bounded Model Checking with Symbolic Counterexamples. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(2): 696-705 (2011) - [j5]Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:
An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(7): 1519-1529 (2011) - [c13]Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:
On-chip dynamic signal sequence slicing for efficient post-silicon debugging. ASP-DAC 2011: 719-724 - 2010
- [j4]Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita:
Performance Estimation with Automatic False-Path Detection for System-Level Designs. IPSJ Trans. Syst. LSI Des. Methodol. 3: 69-80 (2010) - [c12]Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:
Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging. ICCD 2010: 402-408 - [c11]William Newman, David Franzel, Takeshi Matsumoto, Richard Leibbrandt, Trent W. Lewis, Martin H. Luerssen, David M. W. Powers:
Hybrid world object tracking for a virtual teaching agent. IJCNN 2010: 1-9 - [c10]Masahiro Fujita, Hideo Tanida, Fei Gao, Tasuku Nishihara, Takeshi Matsumoto:
Synthesis and formal verification of on-chip protocol transducers through decomposed specification. ISQED 2010: 515-523
2000 – 2009
- 2009
- [j3]Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath. IEICE Trans. Inf. Syst. 92-D(5): 972-984 (2009) - [c9]Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
A Post-Silicon Debug Support Using High-Level Design Description. Asian Test Symposium 2009: 137-142 - 2008
- [c8]Yoshihisa Kojima, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-Level Designs. ATS 2008: 315-320 - [c7]Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
Multi-level Bounded Model Checking to detect bugs beyond the bound. HLDVT 2008: 49-55 - [c6]Masahiro Fujita, Takeshi Matsumoto, Hiroaki Yoshida:
A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams. ICSOFT (SE/MUSE/GSDCA) 2008: 240-245 - 2007
- [c5]Takeshi Matsumoto, Daisuke Ando, Tasuku Nishihara, Masahiro Fujita:
Development and Verification of a Collaborative Printing Environment. C5 2007: 99-108 - 2006
- [j2]Toru Hyakutake, Takeshi Matsumoto, Shinichiro Yanase:
Lattice Boltzmann simulation of blood cell behavior at microvascular bifurcations. Math. Comput. Simul. 72(2-6): 134-140 (2006) - [c4]Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis. HLDVT 2006: 162-169 - [c3]Yuki Suga, Chihiro Endo, Daizo Kobayashi, Takeshi Matsumoto, Shigeki Sugano, Tetsuya Ogata:
Adaptive Human-Robot Interaction System using Interactive EC. IROS 2006: 3663-3668 - [c2]Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita:
Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs. ISQED 2006: 370-375 - 2005
- [j1]Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita:
An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3315-3323 (2005) - 2003
- [c1]Takeshi Matsumoto, David M. W. Powers, Geoff A. Jarrad:
Application of search algorithms to natural language processing. ALTA 2003: 22-29
Coauthor Index
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