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ORCIDDan W. Hammerstrom
Person information
- affiliation: Portland State University, OR, USA
- affiliation: Oregon Graduate Institute, Beaverton, OR, USA
- affiliation (PhD): University of Illinois at Urbana-Champaign, IL, USA
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2010 – 2019
- 2019
[c14]Aakanksha Mathuria, Dan W. Hammerstrom:
Approximate Pattern Matching using Hierarchical Graph Construction and Sparse Distributed Representation. ICONS 2019: 21:1-21:10- 2015
- [j11]Dan Hammerstrom, Vijaykrishnan Narayanan:
Introduction to Special Issue on Neuromorphic Computing. ACM J. Emerg. Technol. Comput. Syst. 11(4): 32:1-32:2 (2015) - 2011
- [j10]Khaldoon M. Mhaidat, Marwan A. Jabri, Daniel W. Hammerstrom:
Representation, methods, and circuits for time-based conversion and computation. Int. J. Circuit Theory Appl. 39(3): 299-311 (2011) - [j9]Mazad S. Zaveri
, Dan W. Hammerstrom:
Performance/price estimates for cortex-scale hardware: A design space exploration. Neural Networks 24(3): 291-304 (2011)
2000 – 2009
- 2008
- [c13]Dan Hammerstrom, Mazad Zaveri:
Bayesian Memory, a Possible Hardware Building Block for Intelligent Systems. AAAI Fall Symposium: Biologically Inspired Cognitive Architectures 2008: 81 - [c12]Changjian Gao, Mazad S. Zaveri, Dan W. Hammerstrom:
CMOS / CMOL architectures for spiking cortical column. IJCNN 2008: 2441-2448 - 2007
- [j8]R. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram:
Architectures for Silicon Nanoelectronics and Beyond. Computer 40(1): 25-33 (2007) - [j7]Changjian Gao, Dan W. Hammerstrom:
Cortical Models Onto CMOL and CMOS - Architectures and Performance/Price. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2502-2515 (2007) - [i1]William N. N. Hung, Changjian Gao, Xiaoyu Song, Dan W. Hammerstrom:
Defect-Tolerant CMOL Cell Assignment via Satisfiability. CoRR abs/0705.4320 (2007) - 2005
- [c11]John D. Lynch, Daniel W. Hammerstrom, Roy Kravitz:
A Cohesive FPGA-Based System-on-Chip Design Curriculum. MSE 2005: 17-18 - 2004
- [j6]Michael P. Arnold, Terrence J. Sejnowski, Dan Hammerstrom, Marwan JA. abri:
Neural systems integration. Neurocomputing 58-60: 1123-1128 (2004) - 2000
- [c10]Dan W. Hammerstrom:
Computational Neurobiology Meets Semiconductor Engineering. ISMVL 2000: 3-14
1990 – 1999
- 1996
- [j5]Dan W. Hammerstrom, Daniel P. Lulich:
Image processing using one-dimensional processor arrays. Proc. IEEE 84(7): 1005-1018 (1996) - 1995
- [c9]Steven Rehfuss, Dan W. Hammerstrom:
Model Matching and SFMD Computation. NIPS 1995: 713-719 - 1993
- [j4]Dan W. Hammerstrom, Steven Rehfuss:
Neurocomputing hardware: present and future. Artif. Intell. Rev. 7(5): 285-300 (1993) - [c8]Dean W. Mueller, Dan Hammerstrom:
A neural network systems component. ICNN 1993: 1258-1264 - 1991
- [c7]Nikolaos G. Bourbakis, Robin Williams, Forouzan Golshani, Myron Flickner, Ted Laliotis, Sukhan Lee, José G. Delgado-Frias, Dan Hammerstrom, Cris Koutsougeras, Gerald G. Pechanek, Benjamin W. Wah, John Yen, Farokh B. Bastani, Tom Cooper, Karan Harbison-Briggs, Rudy Lauber, Alun D. Preece, Imran A. Zualkernan, W. T. Tsai, Daniel E. Cooke, Martin S. Feather, Stephen Fickas, N. Minsky, Peter G. Selfridge, Douglas Smith:
AI in multimedia (panel session). ICTAI 1991: 3-12 - 1990
- [c6]Todd K. Leen, Mike Rudnick, Dan Hammerstrom:
Hebbian feature discovery improves classifier efficiency. IJCNN 1990: 51-56 - [c5]Dan W. Hammerstrom:
A VLSI architecture for high-performance, low-cost, on-chip learning. IJCNN 1990: 537-544
1980 – 1989
- 1988
- [j3]Norm May, Dan Hammerstrom:
Fault simulation of a wafer-scale integrated neural network. Neural Networks 1(Supplement-1): 393-395 (1988) - [j2]Mike Rudnick, Dan Hammerstrom:
An interconnect structure for wafer scale neurocomputers. Neural Networks 1(Supplement-1): 405 (1988) - [c4]Jim Bailey, Dan Hammerstrom:
Why VLSI implementations of associative VLCNs require connection multiplexing. ICNN 1988: 173-180 - 1987
- [c3]Dan W. Hammerstrom:
The Connectivity Analysis of Simple Association. NIPS 1987: 338-347 - 1986
- [j1]Dan Hammerstrom, David Maier, Shreekant S. Thakkar:
The cognitive architecture project. SIGARCH Comput. Archit. News 14(1): 9-21 (1986) - 1982
- [c2]Fred J. Pollack, George W. Cox, Dan W. Hammerstrom, Kevin C. Kahn, Konrad K. Lai, Justin R. Rattner:
Supporting Ada Memory Management in the iAPX-432. ASPLOS 1982: 117-131
1970 – 1979
- 1977
- [b1]Daniel W. Hammerstrom:
Analysis of Memory Addressing Architecture. University of Illinois Urbana-Champaign, USA, 1977 - [c1]Dan W. Hammerstrom, Edward S. Davidson:
Information Content of CPU Memory Referencing Behavior. ISCA 1977: 184-192
Coauthor Index
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