Cryogenic Circuit Performance Prediction Using Design-Oriented Model (SEKV) On 22nm FDSOI - Brian Martinez; Hung-Chi Han; Flávio Enrico Bergamaschi; Quentin Schmidt; Antoine Faurie; Edoardo Charbon; Yvain Thonnart; Baptiste Jadot; Xavier Jehl; Mikaël Cassé; Christian C. Enz; Franck Badets (IEEE International Symposium on Circuits and Systems, ISCAS 2025, London, United Kingdom, May 25-28, 2025, 2025)

13.5 An 18.5\(μ\)W/qubit Cryo-CMOS Charge-Readout IC Demonstrating QAM Multiplexing for Spin Qubits - Quentin Schmidt; Baptiste Jadot; Brian Martinez; Antoine Faurie; Tristan Meunier; Jean-Baptiste Casanova; Xavier Jehl; Yvain Thonnart; Franck Badets (IEEE International Solid-State Circuits Conference, ISSCC 2025, San Francisco, CA, USA, February 16-20, 2025, 2025)

Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro - Bastien Giraud; Sebastien Ricavy; Cyrille Laffond; Ilan Sever; Valentin Gherman; Florent Lepin; Mariam Diallo; Khadija Zenati; Sylvain Dumas; Olivier Guille; Maxim Vershkov; Alessandro Bricalli; et al. (IEEE J. Solid State Circuits, 2024)

A 7.4\(μ\)W and 860\(μ\)m\(^2\)per Channel Cryo-CMOS IC for 70-Channel Frequency-Multiplexed \(μ\)s-Readout of Semiconductor Qubits - Quentin Schmidt; Brian Martinez; Thomas Houriez; Baptiste Jadot; Aloysius G. M. Jansen; Xavier Jehl; Tristan Meunier; Gaël Pillonnet; Gérard Billiot; Adrien Morel; Yvain Thonnart; Franck Badets (IEEE Custom Integrated Circuits Conference, CICC 2024, Denver, CO, USA, April 21-24, 2024, 2024)

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration - Ivan Miro-Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Guillaume Waltener; Emmanuel Pluchart; Jean-Philippe Noel; Adam Makosiej; et al. (IEEE J. Solid State Circuits, 2023)

A Cryogenic Active Router for Qubit Array Biasing from DC to 320 MHz at 100 nm Gate Pitch - Baptiste Jadot; Marcos Zurita; Gérard Billiot; Yvain Thonnart; Loïck Le Guevel; Mathieu Darnas; Candice Thomas; Jean Charbonnier; Tristan Meunier; Maud Vinet; Franck Badets; Gaël Pillonnet (49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, September 11-14, 2023, 2023)

Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro - Bastien Giraud; Sebastien Ricavy; Yasser Moursy; Cyrille Laffond; Ilan Sever; Valentin Gherman; Manuel Pezzin; Florent Lepin; Mariam Diallo; Khadija Zenati; Sylvain Dumas; Maxim Vershkov; et al. (IEEE International Memory Workshop, IMW 2023, Monterey, CA, USA, May 21-24, 2023, 2023)

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration - Ivan Miro-Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Guillaume Waltener; Emmanuel Pluchart; Jean-Philippe Noel; Adam Makosiej; et al. (CoRR, 2023)

Architecting Optically Controlled Phase Change Memory - Aditya Narayan; Yvain Thonnart; Pascal Vivet; Ayse K. Coskun; Ajay Joshi (ACM Trans. Archit. Code Optim., 2022)

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; César Fuguet Tortolero; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (IEEE J. Solid State Circuits, 2021)

PROWAVES: Proactive Runtime Wavelength Selection for Energy-Efficient Photonic NoCs - Aditya Narayan; Yvain Thonnart; Pascal Vivet; Ayse K. Coskun (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration - Alicia Klinefelter; Huichu Liu; Luca Benini; Yvain Thonnart; Keith A. Bowman; Kathy Wilcox; David Bol; Alvin Loke; Ofer Shacham (IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021, 2021)

Designing a Multi-Chiplet Manycore System using the POPSTAR Optical NoC Architecture (Invited) - Yvain Thonnart (ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2021, Munich, Germany, November 4, 2021, 2021)

Architecting Optically-Controlled Phase Change Memory - Aditya Narayan; Yvain Thonnart; Pascal Vivet; Ayse K. Coskun; Ajay Joshi (CoRR, 2021)

System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive Applications - Aditya Narayan; Yvain Thonnart; Pascal Vivet; Ajay Joshi; Ayse K. Coskun (2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Grenoble, France, March 9-13, 2020, 2020)

POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems - Yvain Thonnart; Stéphane Bernabé; Jean Charbonnier; Christian Bernard; David Coriat; César Fuguet Tortolero; Pierre Tissier; Benoît Charbonnier; Stéphane Malhouitre; Damien Saint-Patrice; Myriam Assous; Aditya Narayan; et al. (2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Grenoble, France, March 9-13, 2020, 2020)

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm\(^2\) Inter-Chiplet Interconnects and 156mW/mm\(^2\)@ 82%-Peak-Efficiency DC-DC Converters - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; Guillaume Moritz; Ivan Miro-Panades; César Fuguet Tortolero; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020, 2020)

19.2 A 110mK 295\(μ\)W 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot - Loïck Le Guevel; Gérard Billiot; Xavier Jehl; Silvano De Franceschi; Marcos Zurita; Yvain Thonnart; Maud Vinet; Marc Sanquer; Romain Maurand; Aloysius G. M. Jansen; Gaël Pillonnet (2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020, 2020)

Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone - Yvain Thonnart; Pascal Vivet; Shikhanshu Agarwal; Ramesh Chauhan (25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019, 2019)

WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs - Aditya Narayan; Yvain Thonnart; Pascal Vivet; César Fuguet Tortolero; Ayse K. Coskun (Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019, 2019)

A 10Gb/s Si-photonic transceiver with 150\(μ\)W 120\(μ\)s-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm\(^2\) Die-to-Die Optical Networks - Yvain Thonnart; Mounir Zid; Jose-Luis Gonzalez Jimenez; Guillaume Waltener; Robert Polster; Olivier Dubray; Florent Lepin; Stéphane Bernabé; Sylvie Menezo; Gabriel Pares; Olivier Castany; Laura Boutafa; et al. (2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, 2018)

A 4 exttimes 4 exttimes 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Cristiano Santos; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Denis Dutoit; Fabien Clermidy; Séverine Cheramy; et al. (IEEE J. Solid State Circuits, 2017)

In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization - Ivan Miro Panades; Edith Beigné; Olivier Billoint; Yvain Thonnart (23rd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2017, Thessaloniki, Greece, July 3-5, 2017, 2017)

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks - Luan H. K. Duong; Zhehui Wang; Mahdi Nikdast; Jiang Xu; Peng Yang; Zhifei Wang; Zhe Wang; Rafael K. V. Maeda; Haoran Li; Xuan Wang; Sébastien Le Beux; Yvain Thonnart (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes - Robert Polster; Yvain Thonnart; Guillaume Waltener; Jose-Luis Gonzalez Jimenez; Eric Cassan (IEEE Trans. Very Large Scale Integr. Syst., 2016)

8.1 A 4 exttimes4 exttimes2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Cristiano Santos; Fabien Clermidy; Séverine Cheramy; Frédéric Pétrot; et al. (2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, 2016)

10 Gbps, 560 fJ/b TIA and modulator driver for optical networks-on-chip in CMOS 65nm - Jose-Luis Gonzalez Jimenez; Robert Polster; Guillaume Waltener; Yvain Thonnart; Eric Cassan (14th IEEE International New Circuits and Systems Conference, NEWCAS 2016, Vancouver, BC, Canada, June 26-29, 2016, 2016)

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking - Edith Beigné; Alexandre Valentian; Ivan Miro Panades; Robin Wilson; Philippe Flatresse; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; et al. (IEEE J. Solid State Circuits, 2015)

3D advanced integration technology for heterogeneous systems - Pascal Vivet; Christian Bernard; Fabien Clermidy; Denis Dutoit; Eric Guthmuller; Ivan Miro Panades; Gaël Pillonnet; Yvain Thonnart; Arnaud Garnier; Didier Lattard; Amandine Jouve; Franck Bana; et al. (2015 International 3D Systems Integration Conference, 3DIC 2015, Sendai, Japan, August 31 - September 2, 2015, 2015)

Two-phase protocol converters for 3D asynchronous 1-of-n data links - Julian J. H. Pontes; Pascal Vivet; Yvain Thonnart (The 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, January 19-22, 2015, 2015)

Complementary communication path for energy efficient on-chip optical interconnects - Hui Li; Sébastien Le Beux; Yvain Thonnart; Ian O'Connor (Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015)

Coherent crosstalk noise analyses in ring-based optical interconnects - Luan H. K. Duong; Mahdi Nikdast; Jiang Xu; Zhehui Wang; Yvain Thonnart; Sébastien Le Beux; Peng Yang; Xiaowen Wu; Zhifei Wang (Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015)

Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes - Edith Beigné; Fabien Clermidy; Didier Lattard; Ivan Miro Panades; Yvain Thonnart; Pascal Vivet (2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, 2015)

Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects - Pascal Vivet; Christian Bernard; Eric Guthmuller; Ivan Miro Panades; Yvain Thonnart; Fabien Clermidy (2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 8-10, 2015, 2015)

A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC - Ivan Miro Panades; Edith Beigné; Yvain Thonnart; Laurent Alacoque; Pascal Vivet; Suzanne Lesecq; Diego Puschini; Anca Molnos; Farhat Thabet; Benoît Tain; Karim Ben Chehida; Sylvain Engels; et al. (IEEE J. Solid State Circuits, 2014)

27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking - Robin Wilson; Edith Beigné; Philippe Flatresse; Alexandre Valentian; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; Anuj Grover; et al. (2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014, 2014)

Introduction to the special session on "Silicon photonic interconnects: an illusion or a realistic solution?" - Jiang Xu; Sébastien Le Beux; Yvain Thonnart (Eighth IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, Ferrara, Italy, September 17-19, 2014, 2014)

Technology assessment of silicon interposers for manycore SoCs: Active, passive, or optical? - Yvain Thonnart; Mounir Zid (Eighth IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, Ferrara, Italy, September 17-19, 2014, 2014)

An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip - Sahar Foroutan; Yvain Thonnart; Frédéric Pétrot (IEEE Trans. Computers, 2013)

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs - Edith Beigné; Alexandre Valentian; Bastien Giraud; Olivier Thomas; Thomas Benoist; Yvain Thonnart; Serge Bernard; Guillaume Moritz; Olivier Billoint; Y. Maneglia; Philippe Flatresse; Jean-Philippe Noel; et al. (Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, 2013)

A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC - Edith Beigné; Ivan Miro-Panades; Yvain Thonnart; Laurent Alacoque; Pascal Vivet; Suzanne Lesecq; Diego Puschini; Farhat Thabet; Benoît Tain; K. Benchehida; Sylvain Engels; Robin Wilson; et al. (ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference, Bucharest, Romania, September 16-20, 2013, 2013)

Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology - Bertrand Pelloux-Prayer; Alexandre Valentian; Bastien Giraud; Yvain Thonnart; Jean-Philippe Noel; Philippe Flatresse; Edith Beigné (21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013, 2013)

A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits - Yvain Thonnart; Edith Beigné; Pascal Vivet (18th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2012, Kgs. Lyngby, Denmark, May 7-9, 2012, 2012)

3D NoC using through silicon Via: An asynchronous implementation - Pascal Vivet; Denis Dutoit; Yvain Thonnart; Fabien Clermidy (IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011, 2011)

A fully-asynchronous low-power framework for GALS NoC integration - Yvain Thonnart; Pascal Vivet; Fabien Clermidy (Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, 2010)

An analytical method for evaluating Network-on-Chip performance - Sahar Foroutan; Yvain Thonnart; Richard Hersemeule; Ahmed Jerraya (Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, 2010)

A Markov chain based method for NoC end-to-end latency evaluation - Sahar Foroutan; Yvain Thonnart; Richard Hersemeule; Ahmed Jerraya (24th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010, Atlanta, Georgia, USA, 19-23 April 2010 - Workshop Proceedings, 2010)

A 477mW NoC-based digital baseband for MIMO 4G SDR - Fabien Clermidy; Christian Bernard; Romain Lemaire; Jérôme Martin; Ivan Miro Panades; Yvain Thonnart; Pascal Vivet; Norbert Wehn (IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010, 2010)

Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms - Yvain Thonnart; Romain Lemaire; Fabien Clermidy (NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010, 2010)

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application - Xuan-Tu Tran; Yvain Thonnart; Jean Durupt; Vincent Beroulle; Chantal Robach (IET Comput. Digit. Tech., 2009)

An Asynchronous Power Aware and Adaptive NoC Based Circuit - Edith Beigné; Fabien Clermidy; Hélène Lhermet; Sylvain Miermont; Yvain Thonnart; Xuan-Tu Tran; Alexandre Valentian; Didier Varreau; Pascal Vivet; Xavier Popon; Hugo Lebreton (IEEE J. Solid State Circuits, 2009)

Power Reduction of Asynchronous Logic Circuits Using Activity Detection - Yvain Thonnart; Edith Beigné; Alexandre Valentian; Pascal Vivet (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Design and Implementation of a GALS Adapter for ANoC Based Architectures - Yvain Thonnart; Edith Beigné; Pascal Vivet (15th IEEE Symposium on Asynchronous Circuits and Systems, ASYNC 2009, Chapel Hill, NC, USA, May 17-20, 2009, 2009)

An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application - Fabien Clermidy; Romain Lemaire; Xavier Popon; Dimitri Ktenas; Yvain Thonnart (12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece, 2009)

A Communication and configuration controller for NoC based reconfigurable data flow architecture - Fabien Clermidy; Romain Lemaire; Yvain Thonnart; Pascal Vivet (Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings, 2009)

Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction - Yvain Thonnart; Edith Beigné; Alexandre Valentian; Pascal Vivet (14th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2008, Newcastle upon Tyne, UK, April 7-10, 2008, 2008)

Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures - Nicolas Coste; Hubert Garavel; Holger Hermanns; Richard Hersemeule; Yvain Thonnart; Meriem Zidouni (Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008)

A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application - Xuan-Tu Tran; Yvain Thonnart; Jean Durupt; Vincent Beroulle; Chantal Robach (Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, 2008)

Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip - Gwen Salaün; Wendelin Serwe; Yvain Thonnart; Pascal Vivet (13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California, USA, 2007)

Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip - Xuan-Tu Tran; Jean Durupt; Yvain Thonnart; François Bertrand; Vincent Beroulle; Chantal Robach (First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, 2007)

ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC - Cedric Koch-Hofer; Marc Renaudin; Yvain Thonnart; Pascal Vivet (First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, 2007)