TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes - Arindam Mallik; Paul Zuber; Tsung-Te Liu; Bharani Chava; Bhavana Ballal; Pablo Royer Del Bario; Rogier Baert; Kris Croes; Julien Ryckaert; Mustafa Badaroglu; Abdelkarim Mercha; Diederik Verkest (The 50th Annual Design Automation Conference 2013, DAC '13, Austin, TX, USA, May 29 - June 07, 2013, 2013)

Analysis of FinFET technology on memories - Esteve Amat; A. Asenov; Ramon Canal; Binjie Cheng; J.-Ll. Cruz; Zoran Jaksic; Miguel Miranda; Antonio Rubio; Paul Zuber (18th IEEE International On-Line Testing Symposium, IOLTS 2012, Sitges, Spain, June 27-29, 2012, 2012)

Variability Aware Sub-Wavelength Lithography Characterization for Robust SRAM Design - Petr Dobrovolný; Miguel Miranda; Paul Zuber (ARCS 2011 - 24th International Conference on Architecture of Computing Systems 2011, Workshop Proceedings, February 22-23, 2011, Como, Italy, 2011)

Variability aware modeling for yield enhancement of SRAM and logic - Miguel Miranda; Paul Zuber; Petr Dobrovolný; Philippe Roussel (Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, 2011)

New reliability mechanisms in memory design for sub-22nm technologies - Nivard Aymerich; A. Asenov; Andrew R. Brown; Ramon Canal; Binjie Cheng; Joan Figueras; Antonio González; Enric Herrero; S. Markov; Miguel Miranda; Peyman Pouyan; Tanausú Ramírez; et al. (17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011)

TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies - Ramon Canal; Antonio Rubio; A. Asenov; A. Brown; Miguel Miranda; Paul Zuber; Antonio González; Xavier Vera (Proceedings of the 2nd European Future Technologies Conference and Exhibition, FET 2011, Budapest, Hungary, May 4-6, 2011, 2011)

Optimal wire ordering and spacing in low power semiconductor design - Peter Gritzmann; Michael Ritter; Paul Zuber (Math. Program., 2010)

A holistic approach for statistical SRAM analysis - Paul Zuber; Petr Dobrovolný; Miguel Miranda (Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, 2010)

Statistical SRAM analysis for yield enhancement - Paul Zuber; Miguel Miranda; Petr Dobrovolný; Koen van der Zanden; Jong-Hoon Jung (Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, 2010)

Wire Topology Optimization for Low Power CMOS - Paul Zuber; Othman Bahlous; Thomas Ilnseher; Michael Ritter; Walter Stechele (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Variability aware modeling of SoCs: From device variations to manufactured system yield - Miguel Miranda; Bart Dierickx; Paul Zuber; Petr Dobrovolný; F. Kutscherauer; Philippe Roussel; Pavel Poliakov (10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, 2009)

Exponent Monte Carlo for Quick Statistical Circuit Simulation - Paul Zuber; Vladimir Matvejev; Philippe Roussel; Petr Dobrovolný; Miguel Miranda (Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers, 2009)

Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization - Paul Zuber; Armin Windschiegl; Raúl Medina Beltrán de Otálora; Walter Stechele; Andreas Herkersdorf (2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, 2005)

Optimization Potential of CMOS Power by Wire Spacing - Paul Zuber; Florian Helmut Müller; Walter Stechele (35. Jahrestagung der Gesellschaft für Informatik, Informatik LIVE!, INFORMATIK 2005, Bonn, Germany, September 19-22, 2005, Band 1, 2005)

The Optimal Wire Order for Low Power CMOS - Paul Zuber; Peter Gritzmann; Michael Ritter; Walter Stechele (Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, 2005)

A wire load model considering metal layer properties - Armin Windschiegl; Torsten Mahnke; Michael Eiermann; Walter Stechele; Paul Zuber (Proceedings of the 2002 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002, Dubrovnik, Croatia, September 15-18, 2002, 2002)

Exploiting Metal Layer Characteristics for Low-Power Routing - Armin Windschiegl; Paul Zuber; Walter Stechele (Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, 2002)