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ORCIDDinesh Bhatia
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2020 – today
- 2023
[j22]Pingakshya Goswami
, Dinesh Bhatia:
Application of Machine Learning in FPGA EDA Tool Development. IEEE Access 11: 109564-109580 (2023)- [j21]Ganesh Roy, Dinesh Bhatia, Subhasis Bhaumik:
Feed Forward Neural Network BCI-based trajectory-controlled Lower-limb exoskeleton: a Biomechatronics Approach. Int. J. Robotics Autom. 38(6): 430-440 (2023) - [j20]Pingakshya Goswami, Benjamin Carrión Schäfer, Dinesh Bhatia:
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis. Integr. 88: 116-124 (2023) - [c64]Dinesh Bhatia, Henrik Hesse:
Enhancing Student Engagement in Engineering and Education Through Virtual Reality: A Survey-Based Analysis. TENCON 2023: 170-175 - 2022
- [c63]Pingakshya Goswami, Dinesh Bhatia:
Predicting Post-Route Quality of Results Estimates for HLS Designs using Machine Learning. ISQED 2022: 45-50 - [c62]Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia:
MLSBench: A Benchmark Set for Machine Learning based FPGA HLS Design Flows. LASCAS 2022: 1-4 - [c61]Masoud Shahshahani, Dinesh Bhatia:
PPA Based CNN Architecture Explorer. LASCAS 2022: 1-4 - [c60]Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia:
Robust Estimation of FPGA Resources and Performance from CNN Models. VLSID 2022: 144-149 - [i2]Pingakshya Goswami, Dinesh Bhatia:
Predicting Post-Route Quality of Results Estimates for HLS Designs using Machine Learning. CoRR abs/2205.12397 (2022) - 2021
- [c59]Masoud Shahshahani, Dinesh Bhatia:
Resource and Performance Estimation for CNN Models using Machine Learning. ISVLSI 2021: 43-48 - [c58]Masoud Shahshahani, Mohammad Sabri Abrebekoh, Bahareh Khabbazan, Dinesh Bhatia:
An Automated Tool for Implementing Deep Neural Networks on FPGA. VLSID 2021: 322-327 - 2020
- [j19]Gajendra Kumar Mourya, Dinesh Bhatia, Akash Handique:
Empirical greedy machine-based automatic liver segmentation in CT images. IET Image Process. 14(14): 3333-3340 (2020) - [c57]Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia:
MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows. FPGA 2020: 312 - [i1]Pingakshya Goswami, Dinesh Bhatia:
Automated Floorplanning for Partially Reconfigurable Designs on Heterogenrous FPGAs. CoRR abs/2011.11716 (2020)
2010 – 2019
- 2017
- [c56]Athul Asokan Thulasi, Dinesh Bhatia, Poras T. Balsara, Shalini Prasad:
Portable impedance measurement device for sweat based glucose detection. BSN 2017: 63-66 - 2016
- [j18]Shilpi Mathur, Manvinder Kaur, Dinesh Bhatia, Suresh Verma:
Comparison of muscle activation patterns among healthy males and females during different lower limb movements. Int. J. Medical Eng. Informatics 8(4): 301-316 (2016) - [c55]Pingakshya Goswami, Dinesh Bhatia:
Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only). FPGA 2016: 275 - 2014
- [j17]Abhishek Agarwal, Dinesh Bhatia:
Quantitative measurement of carbon monoxide level in closed environment. Int. J. Medical Eng. Informatics 6(3): 210-217 (2014) - [j16]Devender Singh, Manvinder Kaur, Dinesh Bhatia:
Design of smart functional electric stimulator for physically challenged person. Int. J. Medical Eng. Informatics 6(3): 258-265 (2014) - [j15]Anu, Dinesh Bhatia:
A smart door access system using finger print biometric system. Int. J. Medical Eng. Informatics 6(3): 274-280 (2014) - 2013
- [j14]Aruna Tyagi, Manoj Duhan, Dinesh Bhatia:
Impact of communication technology on human brain activity: mobile phone vs. landline phone. Int. J. Medical Eng. Informatics 5(1): 20-30 (2013) - [j13]Dinesh Bhatia:
Growth of neural engineering and neuro-mechanics in India: physically challenged looking towards a bright future. Int. J. Medical Eng. Informatics 5(3): 201-208 (2013) - [c54]Dinesh Bhatia, A. L. Praveen Aroul:
Antenna designs for wearable body sensor communication. PETRA 2013: 13:1-13:7 - 2011
- [c53]A. L. Praveen Aroul, Dinesh Bhatia:
Study of performance and propagation characteristics of wire and planar structures around human body. EMBC 2011: 4014-4017
2000 – 2009
- 2008
- [c52]Shilpa Bhoj, Dinesh Bhatia:
A dynamic temperature control simulation system for FPGAs. FPL 2008: 659-662 - [c51]Shilpa Bhoj, Dinesh Bhatia:
Early stage FPGA interconnect leakage power estimation. ICCD 2008: 438-443 - [c50]A. L. Praveen Aroul, Achutan Manohar, Dinesh Bhatia, Leonardo Estevez:
Power efficient multi-band contextual activity monitoring for assistive environments. PETRA 2008: 19 - 2007
- [c49]Shilpa Bhoj, Dinesh Bhatia:
Pre-route Interconnect Capacitance and Power Estimation in FPGAs. FPL 2007: 159-164 - [c48]Shilpa Bhoj, Dinesh Bhatia:
Thermal Modeling and Temperature Driven Placement for FPGAs. ISCAS 2007: 1053-1056 - 2006
- [j12]PariVallal Kannan, Dinesh Bhatia:
Interconnect estimation for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8): 1523-1534 (2006) - [c47]Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara:
Generic Network Interfaces for Plug and Play NoC Based Architecture. ARC 2006: 287-298 - [c46]Narayan Subramanian, Rajarshee P. Bharadwaj, Dinesh Bhatia:
A leakage aware design methodology for power-gated programmable architectures. FPT 2006: 301-304 - [c45]Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara:
Exploring Logic Block Granularity in Leakage Tolerant FPGA. VLSI Design 2006: 754-757 - 2005
- [j11]Manjunath Gangadhar, Dinesh Bhatia:
FPGA based EBCOT architecture for JPEG 2000. Microprocess. Microsystems 29(8-9): 363-373 (2005) - [j10]Shankar Balachandran, Dinesh Bhatia:
A priori wirelength and interconnect estimation based on circuit characteristic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1054-1065 (2005) - [c44]Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia:
Exploiting temporal idleness to reduce leakage power in programmable architectures. ASP-DAC 2005: 651-656 - [c43]Shankar Balachandran, Dinesh Bhatia:
Timing Aware Interconnect Prediction Models for FPGAs. FPL 2005: 167-172 - [c42]Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara:
FPGA Architecture for Standby Power Management. FPT 2005: 181-188 - [c41]Mukesh Chugh, Dinesh Bhatia, Poras T. Balsara:
Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA. IPDPS 2005 - [c40]R. Manimegalai, E. Siva Soumya, Vaishnavi Muralidharan, Balaraman Ravindran, V. Kamakoti, Dinesh Bhatia:
Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. VLSI Design 2005: 451-456 - 2004
- [j9]PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
On metrics for comparing interconnect estimation methods for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 381-385 (2004) - [c39]PariVallal Kannan, Dinesh Bhatia:
Estimating Pre-Placement FPGA Interconnection Requirements. VLSI Design 2004: 869- - 2003
- [j8]John Marty Emmert, Sandeep Lodha, Dinesh Bhatia:
On Using Tabu Search for Design Automation of VLSI Systems. J. Heuristics 9(1): 75-90 (2003) - [c38]Manjunath Gangadhar, Dinesh Bhatia:
FPGA based EBCOT architecture for JPEG 2000. FPT 2003: 228-233 - [c37]PariVallal Kannan, Dinesh Bhatia:
Interconnect Estimation for FPGAs under Timing Driven Domains. ICCD 2003: 344-349 - [c36]Shankar Balachandran, Dinesh Bhatia:
A-priori wirelength and interconnect estimation based on circuit characteristics. SLIP 2003: 77-84 - 2002
- [c35]PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
On metrics for comparing routability estimation methods for FPGAs. DAC 2002: 70-75 - [c34]PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
Rapid and Reliable Routability Estimation for FPGAs. FPL 2002: 242-252 - [c33]Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia:
On Routing Demand and Congestion Estimation for FPGAs. ASP-DAC/VLSI Design 2002: 639-646 - 2001
- [c32]PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. FPL 2001: 37-47 - [c31]PariVallal Kannan, Dinesh Bhatia:
Tightly Integrated Placement and Routing for FPGAs. FPL 2001: 233-242 - 2000
- [j7]Dinesh Bhatia, James Haralambides:
Bounds, designs and layouts for multi-terminal FPIC architectures. Integr. 28(2): 141-156 (2000) - [j6]Dinesh Bhatia, James Haralambides:
Resource requirements and layouts for field programmable interconnection chips. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 346-355 (2000)
1990 – 1999
- 1999
- [j5]Karthikeya M. Gajjala Purna, Dinesh Bhatia:
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers. IEEE Trans. Computers 48(6): 579-590 (1999) - [c30]John Marty Emmert, Dinesh Bhatia:
A Methodology for Fast FPGA Floorplanning. FPGA 1999: 47-56 - [c29]John Marty Emmert, Dinesh Bhatia:
Tabu Search: Ultra-Fast Placement for FPGAs. FPL 1999: 81-90 - [c28]Dinesh Bhatia, Kuldeep S. Simha, PariVallal Kannan:
NEBULA: A Partially and Dynamically Reconfigurable Architecture. FPL 1999: 405-410 - [c27]Gregory Tumbush, Dinesh Bhatia:
Clustering to improve bi-partition quality and run time. ISCAS (6) 1999: 145-148 - [c26]John Marty Emmert, Dinesh Bhatia:
Fast timing driven placement using tabu search. ISCAS (1) 1999: 302-305 - 1998
- [c25]Karthikeya M. Gajjala Purna, Dinesh Bhatia:
Temporal Partitioning and Scheduling for Reconfigurable Computing. FCCM 1998: 329-330 - [c24]John Marty Emmert, Akash Randhar, Dinesh Bhatia:
Fast Floorplanning for FPGAs. FPL 1998: 129-138 - [c23]Dinesh Bhatia, PariVallal Kannan, Kuldeep S. Simha, Karthikeya M. Gajjala Purna:
REACT: Reactive Environment for Runtime Reconfiguration. FPL 1998: 209-217 - [c22]Natesan Venkateswaran, Dinesh Bhatia:
Clock-skew constrained placement for row based designs. ICCD 1998: 219-220 - [c21]Karthikeya M. Gajjala Purna, Dinesh Bhatia:
Partitioning in time: a paradigm for reconfigurable computing. ICCD 1998: 340-345 - [c20]Karthikeya M. Gajjala Purna, Dinesh Bhatia:
Emulating Large Designs on Small Reconfigurable Hardware. International Workshop on Rapid System Prototyping 1998: 58-63 - [c19]Raghu Burra, Dinesh Bhatia:
Timing Driven Multi-FPGA Board Partitioning. VLSI Design 1998: 234- - 1997
- [c18]Natesan Venkateswaran, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri:
A constructive method for data path area estimation during high-level VLSI synthesis. ASP-DAC 1997: 509-515 - [c17]Jianzhong Shi, Dinesh Bhatia:
Performance Driven Floorplanning for FPGA Based Designs. FPGA 1997: 112-118 - [c16]John Marty Emmert, Dinesh Bhatia:
Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. FPL 1997: 141-150 - [c15]Gregory Tumbush, Dinesh Bhatia:
Partitioning Under Timing and Area Constraints. ICCD 1997: 614-620 - [c14]Jianzhong Shi, Akash Randhar, Dinesh Bhatia:
Macro Block Based FPGA Floorplanning. VLSI Design 1997: 21-26 - [c13]Dinesh Bhatia:
Reconfigurable Computing. VLSI Design 1997: 356-359 - 1996
- [j4]Dinesh Bhatia, Amit Chowdhary:
A Multi-Terminal Net Router for Field-Programmable Gate Arrays. VLSI Design 4(1): 1-10 (1996) - [j3]Dinesh Bhatia:
Field-Programmable Gate Arrays. VLSI Design 4(4): i-ii (1996) - [j2]Dinesh Bhatia, V. Shankar:
Greedy Segmented Channel Router. VLSI Design 5(1): 11-21 (1996) - [c12]Doug Smith, Dinesh Bhatia:
RACE: Reconfigurable and Adaptive Computing Environment. FPL 1996: 87-95 - [c11]Vijayanand Sankarasubramanian, Dinesh Bhatia:
Multiway Partitioner for High Performance FPGA Based Board Architecture. ICCD 1996: 579-585 - [c10]Natesan Venkateswaran, Dinesh Bhatia:
Clock-Skew Constrained Cell Placement. VLSI Design 1996: 146-149 - 1995
- [j1]Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia:
Pseudo-exhaustive built-in TPG for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1160-1171 (1995) - [c9]Dinesh Bhatia, James Haralambides:
Resource requirements for field programmable interconnection chips. VLSI Design 1995: 376-380 - 1994
- [c8]V. Shankar, Dinesh Bhatia:
Generalized segmented channel routing. Great Lakes Symposium on VLSI 1994: 64-69 - [c7]Dinesh Bhatia, Amit Chowdhary, Spyros Tragoudas:
Mathematical model for routability analysis of FPGAs. Great Lakes Symposium on VLSI 1994: 76-79 - [c6]Amit Chowdhary, Dinesh Bhatia:
Detailed Routing of Multi-Terminal Nets in FPGAs. VLSI Design 1994: 237-242 - [c5]Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori:
Hierarchical Reconfiguration of VLSI/WSI Arrays. VLSI Design 1994: 349-352 - 1993
- [c4]Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia:
Pseudoexhaustive BIST for Sequential Circuits. ICCD 1993: 523-527 - 1992
- [c3]Dinesh Bhatia, Frank Thomson Leighton, Fillia Makedon, Carolyn Haibt Norton:
Improved Algorithms for Routing on Two-Dimensional Grids. WG 1992: 114-122 - 1990
- [c2]Dinesh Bhatia, Frank Thomson Leighton, Fillia Makedon:
Efficient Reconfiguration of WSI Arrays. ICSI 1990: 47-56 - [c1]Dinesh Bhatia:
Restructuring wafers for maximum yield and some applications of WSI. SPDP 1990: 750-753
Coauthor Index
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