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2020 – today
- 2024
[j29]Taewook Kang, Kwang-Il Oh
, Jae-Jin Lee, Sungeun Kim, Woojoo Lee, Wangrok Oh, Seong-Eun Kim:
Anti-Spoofing for Fingerprint Recognition Using Electric Body Pulse Response. IEEE Internet Things J. 11(4): 5993-6006 (2024)- [j28]Eunjin Choi, Jina Park, Kyeongwon Lee, Jae-Jin Lee, Kyuseung Han, Woojoo Lee:
Day-Night architecture: Development of an ultra-low power RISC-V processor for wearable anomaly detection. J. Syst. Archit. 152: 103161 (2024) - [j27]Jina Park, Kyuseung Han, Eunjin Choi, Jae-Jin Lee, Kyeongwon Lee, Woojoo Lee, Massoud Pedram:
Designing Low-Power RISC-V Multicore Processors With a Shared Lightweight Floating Point Unit for IoT Endnodes. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 4106-4119 (2024) - [c24]Hyeonguk Jang, Jae-Jin Lee, Kyuseung Han:
Optimizing Implementation of SNN for Embedded System. ICACT 2024: 104-106 - [c23]Kyuseung Han, Hyunseok Kwak, Kwang-Il Oh, Sukho Lee, Hyeonguk Jang, Jae-Jin Lee, Woojoo Lee:
STARC: Crafting Low-Power Mixed-Signal Neuromorphic Processors by Bridging SNN Frameworks and Analog Designs. ISLPED 2024: 1-6 - 2023
- [c22]Jina Park, Eunjin Choi, Kyungwon Lee, Jae-Jin Lee, Kyuseung Han, Woojoo Lee:
Developing an Ultra-low Power RISC-V Processor for Anomaly Detection. DATE 2023: 1-2 - [c21]Jina Park, Kyuseung Han, Eunjin Choi, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram:
Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU. ISLPED 2023: 1-6 - 2022
- [j26]Taewook Kang, Kwang-Il Oh, Jae-Jin Lee, Sungeun Kim, Seoung-Eun Kim, Woojoo Lee, Wangrok Oh:
Spiking Neural Networks-Inspired Signal Detection Based on Measured Body Channel Response. IEEE Trans. Instrum. Meas. 71: 1-16 (2022) - [c20]In-San Jeon, Hyuk Kim, Jae-Jin Lee:
A Logarithmic Domain Algorithm of the Hodgkin-Huxley Neuron Model for Hardware Implementations. ICEIC 2022: 1-3 - [c19]Taewook Kang, Kwang-Il Oh, Jae-Jin Lee, Wangrok Oh:
Comparison between STDP and Gradient-descent Training Processes for Spiking Neural Networks Using MNIST Digits. ICTC 2022: 1732-1734 - [c18]Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han:
Releasing the Memory Bottleneck to Display Video Correctly. ISOCC 2022: 340-341 - 2021
- [j25]Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee, Seung-Yeong Lee, Jae-Hyoung Lee, Woojoo Lee:
Developing a Multicore Platform Utilizing Open RISC-V Cores. IEEE Access 9: 120010-120023 (2021) - [j24]Kyuseung Han, Sukho Lee, Kwang-Il Oh, Younghwan Bae, Hyeonguk Jang, Jae-Jin Lee, Woojoo Lee, Massoud Pedram:
Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes. IEEE Internet Things J. 8(6): 4642-4656 (2021) - [j23]Yi Wang, Hao Zhang, Kwang-Il Oh, Jae-Jin Lee, Seok-Bum Ko:
Energy efficient spiking neural network processing using approximate arithmetic units and variable precision weights. J. Parallel Distributed Comput. 158: 164-175 (2021) - [j22]Taewook Kang, Jung-Hwan Hwang, Hyuk Kim, Sungeun Kim, Kwang-Il Oh, Jae-Jin Lee, Hyung-Il Park, Seong-Eun Kim, Wangrok Oh, Woojoo Lee:
Measurement and Evaluation of Electric Signal Transmission Through Human Body by Channel Modeling, System Design, and Implementation. IEEE Trans. Instrum. Meas. 70: 1-14 (2021) - [j21]Taewook Kang, Kwang-Il Oh, Jae-Jin Lee, Beom-Su Park, Wangrok Oh, Seong-Eun Kim:
Measurement and Analysis of Human Body Channel Response for Biometric Recognition. IEEE Trans. Instrum. Meas. 70: 1-12 (2021) - 2020
- [j20]Jin-Ho Chung, Taewook Kang, Dohyun Kwun, Jae-Jin Lee, Seong-Eun Kim:
User Recognition Based on Human Body Impulse Response: A Feasibility Study. IEEE Access 8: 6627-6637 (2020) - [j19]Syed Asmat Ali Shah, Saad Arslan, Jae-Jin Lee, Bo-Seok Seo, HyungWon Kim:
A Switched Capacitor Voltage Converter With Exponentially Sized Capacitor Banks for Wide Load Range. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 2049-2053 (2020) - [j18]Taewook Kang, Sungeun Kim, Kwang-Il Oh, Jung-Hwan Hwang, Jae-Jin Lee, Hyungil Park, Kyungjin Byun, Woojoo Lee:
Evaluation of Human Body Characteristics for Electric Signal Transmission Based on Measured Body Impulse Response. IEEE Trans. Instrum. Meas. 69(9): 6399-6411 (2020)
2010 – 2019
- 2019
- [j17]Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee, Woojoo Lee:
MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems. IEEE Access 7: 80011-80019 (2019) - [j16]Kyuseung Han, Jae-Jin Lee, Woojoo Lee, Jinho Lee:
A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties. IEEE Des. Test 36(2): 81-87 (2019) - [j15]Yi Wang, Karim Shahbazi, Hao Zhang, Kwang-Il Oh, Jae-Jin Lee, Seok-Bum Ko:
Efficient spiking neural network training and inference with reduced precision memory and computing. IET Comput. Digit. Tech. 13(5): 397-404 (2019) - [j14]Woojoo Lee, Taewook Kang, Jae-Jin Lee, Kyuseung Han, Joongheon Kim, Massoud Pedram:
TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1758-1770 (2019) - [c17]Kyuseung Han, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram:
TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip Platform. ISLPED 2019: 1-6 - [c16]Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee:
Supporting Serial Interfaces on Virtual SoC Platforms to Develop Sensor Applications. ISOCC 2019: 101-102 - 2018
- [j13]A. N. Ragheb, HyungWon Kim, Jae-Jin Lee:
84% High efficiency dynamic voltage scaler with nano-second settling time based on charge-pump and BWC-DAC. Microelectron. J. 79: 91-97 (2018) - [j12]Kyuseung Han, Jae-Jin Lee, Jinho Lee, Woojoo Lee, Massoud Pedram:
TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 458-471 (2018) - [j11]Saad Arslan, Syed Asmat Ali Shah, Jae-Jin Lee, HyungWon Kim:
An Energy Efficient Charging Technique for Switched Capacitor Voltage Converters With Low-Duty Ratio. IEEE Trans. Circuits Syst. II Express Briefs 65-II(6): 779-783 (2018) - 2017
- [j10]Joongheon Kim, Jae-Jin Lee, Jong-Kook Kim, Woojoo Lee:
Energy-Efficient Stabilized Automatic Control for Multicore Baseband in Millimeter-Wave Systems. IEEE Access 5: 16584-16591 (2017) - [j9]Joongheon Kim, Jae-Jin Lee, Woojoo Lee:
Strategic Control of 60 GHz Millimeter-Wave High-Speed Wireless Links for Distributed Virtual Reality Platforms. Mob. Inf. Syst. 2017: 5040347:1-5040347:10 (2017) - 2015
- [j8]Hyun-Ho Jo, Yong-Jo Ahn, Dae-Beom Kang, Bongil Ji, Dong-Gyu Sim, Jae-Jin Lee:
Flexible Multi-Core Platform for a Multiple-Format Video Decoder. J. Signal Process. Syst. 80(2): 163-179 (2015) - [c15]Jae-Jin Lee, Chan Kim, Kyungjin Byun, Nak-Woong Eum:
Virtual prototype based on Aldebarn CPU core. VLSI-SoC 2015: 303-306 - 2013
- [j7]Jang-Woo Lee, Hong-Jung Kim, Chun-Seok Jeong, Jae-Jin Lee, Changsik Yoo:
Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2155-2159 (2013) - 2012
- [c14]Jae-Jin Lee, Kyungjin Byun, Nak-Woong Eum:
Multi-core architecture for video decoding. ISOCC 2012: 25-28 - [c13]Jongpil Jung, Kyungsu Kang, Jae-Jin Lee, Youngjun Yoon, Chong-Min Kyung:
Cost-effective TSV redundancy configuration. VLSI-SoC 2012: 263-266 - 2011
- [c12]Jae-Jin Lee, Young-Jin Oh, Gi-Yong Song:
Design and verification of an application-specific PLD using VHDL and SystemVerilog. ASICON 2011: 159-162 - [c11]Jae-Jin Lee, Nak-Woong Eum:
Application specific processor for multi-standard video decoding. ISOCC 2011: 436-439 - 2010
- [j6]Jun-Young Lee, Jae-Jin Lee, Seongmo Park:
Multi-core platform for an efficient H.264 and VC-1 video decoding based on macroblock row-level parallelism. IET Circuits Devices Syst. 4(2): 147-158 (2010) - [j5]Jun-Young Lee, Jae-Jin Lee, Seongmo Park:
New Lookup Tables and Searching Algorithms for Fast H.264/AVC CAVLC Decoding. IEEE Trans. Circuits Syst. Video Technol. 20(7): 1007-1017 (2010)
2000 – 2009
- 2009
- [j4]Hae-Kang Jung, Kyoungho Lee, Jong-Sam Kim, Jae-Jin Lee, Jae-Yoon Sim, Hong-June Park:
A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control. IEEE J. Solid State Circuits 44(11): 2891-2900 (2009) - [j3]Young-Suk Seo, Jang-Woo Lee, Hong-Jung Kim, Changsik Yoo, Jae-Jin Lee, Chun-Seok Jeong:
A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-μm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 56-II(1): 6-10 (2009) - 2008
- [c10]Seung Hee Han, Bom Soo Kim, Chan Kyou Hwang, Jae-Jin Lee:
Service Impact Analysis Framework Using Service Model for Integrated Service Resource Management of NGN Services. APNOMS 2008: 433-436 - [c9]Jun-Young Lee, Jae-Jin Lee, MooKyoung Jeong, Nak-Woong Eum, Seongmo Park:
A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder. ISCAS 2008: 3462-3465 - 2007
- [c8]Jae-Jin Lee, Dong-Guk Hwang, Gi-Yong Song:
Design of a Reversible PLD Architecture. ARC 2007: 85-90 - 2006
- [c7]Jae-Jin Lee, Gi-Yong Song:
High-Level Synthesis Using SPARK and Systolic Array. ARC 2006: 455-460 - [c6]Jae-Jin Lee, Gi-Yong Song:
Super Semi-systolic Array-Based Application-Specific PLD Architecture. ARC 2006: 461-466 - 2005
- [j2]Jae-Jin Lee, Gi-Yong Song:
A New Application-Specific PLD Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(6): 1425-1433 (2005) - [c5]Jae-Jin Lee, Gi-Yong Song:
Design of an application-specific PLD architecture. ASP-DAC 2005: 1244-1247 - 2004
- [c4]Chun-Seok Jeong, Changsik Yoo, Jae-Jin Lee, Joongsik Kih:
Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM. ESSCIRC 2004: 379-382 - [c3]Jae-Jin Lee, Gi-Yong Song:
Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier. FPGA 2004: 249 - [c2]Kyung-Ah Han, Jae-Jin Lee, Jae-Cheol Ryou:
The VDSL Deployments and Their Associated Crosstalk with xDSL Systems. ICT 2004: 1296-1302 - 2003
- [c1]Jae-Jin Lee, Gi-Yong Song:
Implementation of the super-systolic array for convolution. ASP-DAC 2003: 491-494
1990 – 1999
- 1997
- [j1]Ho-Jun Song, Jung-Pill Kim, Jae-Jin Lee, Jong-Hoon Oh, Seung-Han Ahn, Inseok Hwang:
A 200 MHz register-based wave-pipelined 64 M synchronous DRAM. IEEE J. Solid State Circuits 32(1): 92-99 (1997)
Coauthor Index
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