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2000 – 2009
- 2009
[j4]Kenneth M. Butler, John M. Carulli Jr., Jayashree Saxena, Amit Nahar, W. Robert Daasch:
Multidimensional Test Escape Rate Modeling. IEEE Des. Test Comput. 26(5): 74-82 (2009)- 2008
- [j3]Srivaths Ravi, Rubin A. Parekhji, Jayashree Saxena:
Low Power Test for Nanometer System-on-Chips (SoCs). J. Low Power Electron. 4(1): 81-100 (2008) - [c14]Kenneth M. Butler, John M. Carulli Jr., Jayashree Saxena:
Modeling Test Escape Rate as a Function of Multiple Coverages. ITC 2008: 1-9 - 2004
- [c13]Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington:
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques. ITC 2004: 355-364 - 2003
- [c12]Jayashree Saxena, Kenneth M. Butler, Vinay B. Jayaram, Subhendu Kundu, N. V. Arvind, Pravin Sreeprakash, Manfred Hachinger:
A Case Study of IR-Drop in Structured At-Speed Testing. ITC 2003: 1098-1104 - 2002
- [c11]Jayashree Saxena, Kenneth M. Butler, John Gatt, R. Raghuraman, Sudheendra Phani Kumar, Supatra Basu, David J. Campbell, John Berech:
Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges . ITC 2002: 1120-1129 - 2001
- [c10]Jayashree Saxena, Kenneth M. Butler, Lee Whetsel:
An analysis of power reduction techniques in scan testing. ITC 2001: 670-677 - 2000
- [c9]Jayashree Saxena, Kenneth M. Butler:
An empirical study on the effects of test type ordering on overall test efficiency. ITC 2000: 408-416 - [c8]Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler:
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. ITC 2000: 729-738
1990 – 1999
- 1998
- [c7]Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess:
On applying non-classical defect models to automated diagnosis. ITC 1998: 748-757 - [c6]Jayashree Saxena:
IC diagnosis: preventing wars and war stories. ITC 1998: 1138 - 1997
- [j2]Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Kinra, Jayashree Saxena:
Automated Diagnosis in Testing and Failure Analysis. IEEE Des. Test Comput. 14(3): 83-89 (1997) - [c5]David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler:
Bridging Fault Diagnosis in the Absence of Physical Information. ITC 1997: 887-893 - 1996
- [c4]Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Jones, Jayashree Saxena:
Integrating Automated Diagnosis into the Testing and Failure Analysis Operations. ITC 1996: 934 - 1995
- [j1]Dhiraj K. Pradhan, Jayashree Saxena:
A novel scheme to reduce test application time in circuits with full scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1577-1586 (1995) - 1993
- [c3]Jayashree Saxena, Dhiraj K. Pradhan:
Desgin for Testability of Asynchronous Sequential Circuits. ICCD 1993: 518-522 - [c2]Jayashree Saxena, Dhiraj K. Pradhan:
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits. ITC 1993: 724-733 - 1992
- [c1]Dhiraj K. Pradhan, Jayashree Saxena:
A design for testability scheme to reduce test application time in full scan. VTS 1992: 55-60
Coauthor Index
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