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2010 – 2019
- 2015
[c40]Min-Kyu Kim, Ju Hee Choi, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Bypassing method for STT-RAM based inclusive last-level cache. RACS 2015: 424-429- 2014
- [j27]Ju Hee Choi
, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Data Filter Cache with Partial Tag Matching for Low Power Embedded Processor. IEICE Trans. Inf. Syst. 97-D(4): 972-975 (2014) - [j26]Ju Hee Choi, Jong Wook Kwak, Chu Shik Jhon:
Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor. IEICE Trans. Inf. Syst. 97-D(8): 2166-2169 (2014) - [c39]Ju Hee Choi, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Adaptive cache compression for non-volatile memories in embedded system. RACS 2014: 52-57 - 2013
- [j25]Young-Sik Eom, Jong Wook Kwak, Seong Tae Jhang, Chu-Shik Jhon:
Bypass Extended Stack Processing for Anti-Thrashing Replacement in Shared Last Level Cache of Chip Multiprocessors. IEICE Trans. Inf. Syst. 96-D(2): 370-374 (2013) - [c38]Ju Hee Choi, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Data filter cache with word selection cache for low power embedded processor. RACS 2013: 422-427 - 2012
- [j24]Young-Sik Eom, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Throttling Capacity Sharing Using Life Time and Reuse Time Prediction in Private L2 Caches of Chip Multiprocessors. IEICE Trans. Inf. Syst. 95-D(6): 1676-1679 (2012) - [c37]Hyun-Bum Cho, Ju Hee Choi, Seong-Tea Jhang, Chu-Shik Jhon:
Low Power Instruction Cache with Word Selective Line Buffer. CSE 2012: 215-222 - 2011
- [j23]Byoung-Soon Jang, Taehyoun Kim, Chu Shik Jhon, Hyo-Joong Suh:
Time-Interleaved Access Control to Common RF Subsystem for Concurrent WiFi and WiMAX. IEICE Trans. Commun. 94-B(7): 2118-2122 (2011) - [c36]Young-Sik Eom, Seong Tae Jhang, Chu-Shik Jhon:
Throttling capacity sharing in private L2 caches of CMPs. RACS 2011: 20-24 - [c35]Yun Kyo Cho, Seong Tae Jhang, Chu Shik Jhon:
Selective word reading for high performance and low power processor. RACS 2011: 25-30 - 2010
- [c34]Jungwook Kim, Seong Tae Jhang, Chu Shik Jhon:
Dynamic register-renaming scheme for reducing power-density and temperature. SAC 2010: 231-237
2000 – 2009
- 2008
- [j22]Soong Hyun Shin, Sung Woo Chung, Eui-Young Chung, Chu Shik Jhon:
Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(7): 1772-1779 (2008) - [j21]Jong Wook Kwak, Chu Shik Jhon:
High-performance embedded branch predictor by combining branch direction history and global branch history. IET Comput. Digit. Tech. 2(2): 142-154 (2008) - 2007
- [j20]Jong Wook Kwak, Chu Shik Jhon:
Dynamic per-branch history length adjustment to improve branch prediction accuracy. Microprocess. Microsystems 31(1): 63-76 (2007) - [j19]Jong Wook Kwak, Chu Shik Jhon:
Torus Ring: improving performance of interconnection network by modifying hierarchical ring. Parallel Comput. 33(1): 2-20 (2007) - 2006
- [j18]Cheol Hong Kim, Sung Woo Chung, Chu Shik Jhon:
An Energy-Efficient Partitioned Instruction Cache Architecture for Embedded Processors. IEICE Trans. Inf. Syst. 89-D(4): 1450-1458 (2006) - [j17]Hyo Jin Choi, Jinhwan Jeon, Taehyoun Kim, Hyo-Joong Suh, Chu Shik Jhon:
Robust Delay Control for Audio Streaming over Wireless Link. IEICE Trans. Inf. Syst. 89-D(8): 2448-2451 (2006) - [j16]Jong Wook Kwak, Cheol Hong Kim, Sung-Hoon Shim, Chu Shik Jhon:
Advanced High-Level Cache Management by Processor Access Information. J. Inf. Sci. Eng. 22(1): 215-227 (2006) - [j15]Jong Wook Kwak, Chu Shik Jhon:
Adaptive Multi-Grain Remote Access Cache in Ring Based NUMA System. J. Inf. Sci. Eng. 22(6): 1543-1554 (2006) - [j14]Cheol Hong Kim, Sung Woo Chung, Chu Shik Jhon:
PP-cache: A partitioned power-aware instruction cache architecture. Microprocess. Microsystems 30(5): 268-279 (2006) - [c33]Soong Hyun Shin, Sung Woo Chung, Chu Shik Jhon:
On the Reliability of Drowsy Instruction Caches. Asia-Pacific Computer Systems Architecture Conference 2006: 445-451 - [c32]Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Accuracy Enhancement by Selective Use of Branch History in Embedded Processor. International Conference on Computational Science (4) 2006: 979-986 - [c31]Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
History Length Adjustable gshare Predictor for High-Performance Embedded Processor. ICCSA (4) 2006: 631-638 - [c30]Jong Wook Kwak, Chu Shik Jhon:
Recovery Logics for Speculative Update Global and Local Branch History. ISCIS 2006: 258-266 - 2005
- [j13]Sung-Joon Park, Myoung-Wan Koo, Chu Shik Jhon:
Context-Dependent Phoneme Duration Modeling with Tree-Based State Tying. IEICE Trans. Inf. Syst. 88-D(3): 662-666 (2005) - [j12]Jong Wook Kwak, Hyong Jin Ban, Chu Shik Jhon:
Torus Ring: Improving Interconnection Network Performance by Modifying Hierarchical Ring. IEICE Trans. Inf. Syst. 88-D(5): 1067-1071 (2005) - [j11]Jong Wook Kwak, Ju-Hwan Kim, Chu Shik Jhon:
The Impact of Branch Direction History Combined with Global Branch History in Branch Prediction. IEICE Trans. Inf. Syst. 88-D(7): 1754-1758 (2005) - [j10]Sung Woo Chung, Hyong-Shik Kim, Chu Shik Jhon:
A Split L2 Data Cache for Scalable Cc-numa Multiprocessors. J. Circuits Syst. Comput. 14(3): 605-618 (2005) - [j9]Cheol Kim, Sung Chung, Chu Shik Jhon:
A Power-Aware Branch Predictor by Accessing the BTB Selectively. J. Comput. Sci. Technol. 20(5): 607-614 (2005) - [j8]Sung Woo Chung, Hyong-Shik Kim, Chu Shik Jhon:
Distance-aware L2 cache organizations for scalable multiprocessor systems. J. Syst. Archit. 51(6-7): 368-381 (2005) - [c29]Cheol Kim, Sung Chung, Chu Shik Jhon:
An Innovative Instruction Cache for Embedded Processors. Asia-Pacific Computer Systems Architecture Conference 2005: 41-51 - [c28]Soong Hyun Shin, Cheol Hong Kim, Chu Shik Jhon:
An Effective Instruction Cache Prefetch Policy by Exploiting Cache History Information. EUC 2005: 57-66 - [c27]Cheol Hong Kim, Sung-Hoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon:
First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption. SAMOS 2005: 103-111 - [c26]Sung-Hoon Shim, Jong Wook Kwak, Cheol Hong Kim, Sung Tae Jhang, Chu Shik Jhon:
Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic. SAMOS 2005: 162-171 - 2004
- [j7]Sung Woo Chung, Hyong-Shik Kim, Chu Shik Jhon:
Utilization of the On-Chip L2 Cache Area in CC-NUMA Multiprocessors for Applications with a Small Working Set. IEICE Trans. Inf. Syst. 87-D(7): 1617-1624 (2004) - [c25]Cheol Hong Kim, Jong Wook Kwak, Seong Tae Jhang, Chu Shik Jhon:
Adaptive Block Management for Victim Cache by Exploiting L1 Cache History Information. EUC 2004: 1-11 - [c24]Sung-Hoon Shim, Cheol Hong Kim, Jong Wook Kwak, Chu Shik Jhon:
Hybrid Technique for Reducing Energy Consumption in High Performance Embedded Processor. EUC 2004: 74-84 - [c23]Cheol Hong Kim, Sung-Hoon Shim, Jong Wook Kwak, Chu Shik Jhon:
A Novel Approach to Improve Cache Performance in Ring-Based Multiprocessors. PDPTA 2004: 519-524 - [c22]Jong Wook Kwak, Hyunbae Lee, Cheol Hong Kim, Sung-Hoon Shim, Chu Shik Jhon:
Level 1 & Victim Cache Management with Processor Reuse Information. PDPTA 2004: 694-698 - [c21]Soong Hyun Shin, Jong Wook Kwak, Chu Shik Jhon:
Ownership-Lacking Line First Policy of Remote Access Cache in NUMA System. PDPTA 2004: 1319-1323 - 2003
- [c20]Sung Woo Chung, Hyong-Shik Kim, Chu Shik Jhon:
Distance-aware L2 Cache Organizations for Scalable Multiprocessor Systems. DSD 2003: 24-32 - 2002
- [j6]Sung Woo Chung, Jeong-Heon Shin, Hyong-Shik Kim, Chu Shik Jhon:
A Second-Level Cache With the Distance-Aware Replacement Policy for NUMA Systems. J. Inf. Sci. Eng. 18(5): 803-813 (2002) - [c19]Joo Beom Yun, Seong Tae Jhang, Chu Shik Jhon, Cheol Won Lee:
Analysis of System Performance by Changing the Ring Architecture on the Dual Ring CC-NUMA System. ICPADS 2002: 103- - [c18]Sung Woo Chung, Chu Shik Jhon, Hyong-Shik Kim:
An Effective L2 Cache Replacement Policy to Distribute the Bus Traffic in the SMP Node. IASTED PDCS 2002: 782-787 - 2001
- [c17]Sung Woo Chung, Hyong-Shik Kim, Chu Shik Jhon:
Accelerating the Continuous Data in a SCI-Based Multimedia System. ICPADS 2001: 171-178 - [c16]Byoung-Soon Jang, Sung Woo Chung, Seong Tae Jhang, Chu Shik Jhon:
Efficient schemes to scale the interconnection network bandwidth in a ring-based multiprocessor system. SAC 2001: 510-516 - 2000
- [j5]Jae Bum Lee, Chu Shik Jhon:
Improving the Execution Efficiency of Barrier Synchronization in Software DSM through Static Analysis. Int. J. High Speed Comput. 11(3): 167-188 (2000) - [c15]Sung Woo Chung, Seong Tae Jhang, Chu Shik Jhon:
Analysis of slotted ring network in real-time systems. CATA 2000: 5-8 - [c14]Hyo Jin Choi, Hyo-Joong Suh, Seong Tae Jhang, Chu Shik Jhon:
A Method for an Integrated Simulation Linked with Scheduling Policies on a Program-Driven Simulator. MASCOTS 2000: 134-141 - [c13]Chul Hong Kim, Seong Tae Jhang, Chu Shik Jhon:
Alternatives to Enhance the Performance of Disk I/O in Ring-Based Multiprocessors. PDPTA 2000
1990 – 1999
- 1999
- [c12]Sung Woo Chung, Chu Shik Jhon:
Optimal Interconnection Network Bandwidth for Ring-Based Multiprocessor Systems. PDPTA 1999: 2266-2271 - 1998
- [j4]Jin-Soo Kim, Soonhoi Ha, Chu Shik Jhon:
Relaxed Barrier Synchronization for the BSP Model of Computation on Message-Passing Architectures. Inf. Process. Lett. 66(5): 247-253 (1998) - [j3]Kyoung-Son Jhang, Soonhoi Ha, Chu Shik Jhon:
Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing. VLSI Design 7(1): 85-95 (1998) - [c11]Sung Woo Chung, Seong Tae Jhang, Chu Shik Jhon:
PANDA: Ring-Based Multiprocessor System Using New Snooping Protocol. ICPADS 1998: 10-17 - [c10]Jin-Soo Kim, Soonhoi Ha, Chu Shik Jhon:
Efficient Barrier Synchronization Mechanism for BSP Model on Message Passing Architectures. IPPS/SPDP 1998: 255-259 - [c9]Jae Bum Lee, Chu Shik Jhon:
Reducing Coherence Overhead of Barrier Synchronization in Software DSMs. SC 1998: 27 - 1997
- [c8]Jae Bum Lee, Chu Shik Jhon:
Hardware Support for Release Consistency with Queue-based Synchronization. ICPADS 1997: 144- - [c7]Hyong-Shik Kim, Soonhoi Ha, Chu Shik Jhon:
Quantitative Analysis on Caching Effect of I-Structure Data in Frame-Based Multithreaded Processing. ICPP 1997: 122-127 - [c6]Jin-Soo Kim, Soonhoi Ha, Chu Shik Jhon:
Reducing Overheads of Local Communications in Fine-grain Parallel Computation. ICPP 1997: 223-226 - 1996
- [j2]Kyoung-Son Jhang, Soonhoi Ha, Chu Shik Jhon:
COP: a Crosstalk OPtimizer for gridded channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(4): 424-429 (1996) - [c5]Kang Yi, Chu Shik Jhon:
A New FPGA Technology Mapping Approach by Cluster Merging. FPL 1996: 366-370 - 1995
- [j1]Seong Yong Ohm, Fadi J. Kurdahi, Chu Shik Jhon:
An Optimal Scheduling Approach Using Lower Bound in High-Level Synthesis. IEICE Trans. Inf. Syst. 78-D(3): 231-236 (1995) - [c4]Sung Tae Jung, Eun Sei Park, Jung Sik Kim, Chu Shik Jhon:
Automatic Synthesis of Gate-Level Speed-Independent Control Circuits from Signal Transition Graphs. ISCAS 1995: 1211-1214 - 1994
- [c3]Sung Tae Jung, Chu Shik Jhon:
Direct Synthesis of Efficient Speed-Independent Circuits from Deterministic Signal Transition Graphs. ISCAS 1994: 307-310 - 1992
- [c2]Myuhng Joo Kim, Chu Shik Jhon, Tetsuo Ida:
G-system: A Functionally-Based Communication System Model for Parallel Processing. IFIP Congress (1) 1992: 170-178 - 1990
- [c1]Myuhng Joo Kim, Chu Shik Jhon:
Functional C: an extended functional programming language. Jerusalem Conference on Information Technology 1990: 298-302
Coauthor Index
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