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ORCIDACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 12
Volume 12, Number 1, January 2007
- Anup Gangwar, M. Balakrishnan, Anshul Kumar:
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. 1:1-1:29 - Nicholas H. Zamora, Xiaoping Hu, Radu Marculescu
:
System-level performance/power analysis for platform-based design of multimedia applications. 2:1-2:29 - Chiu-Wing Sham, Evangeline F. Y. Young:
Area reduction by deadspace utilization on interconnect optimized floorplan. 3:1-3:11 - Lei Li, Zhanglei Wang, Krishnendu Chakrabarty:
Scan-BIST based on cluster analysis and the encoding of repeating sequences. 4:1-4:21 - Yuan Cai, Marcus T. Schmitz, Bashir M. Al-Hashimi, Sudhakar M. Reddy:
Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints. 5:1-5:24 - Xinping Zhu, Sharad Malik:
A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs. 6:1-6:24 - Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das:
Hierarchical partitioning of VLSI floorplans by staircases. 7:1-7:19 - Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt:
Instruction set synthesis with efficient instruction encoding for configurable processors. 9:1-9:37
Volume 12, Number 2, April 2007
- Nikil D. Dutt:
Editorial. 9 - Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta:
Disjunctive image computation for software verification. 10 - Bren Mochocki, Xiaobo Sharon Hu, Gang Quan:
Transition-overhead-aware voltage scheduling for fixed-priority real-time systems. 11 - Hongliang Chang, Sachin S. Sapatnekar:
Prediction of leakage power under process uncertainties. 12 - Sumit Mohanty, Viktor K. Prasanna:
A model-based extensible framework for efficient application design using FPGA. 13 - Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau:
A predictive decode filter cache for reducing power consumption in embedded processors. 14 - Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil D. Dutt:
DRDU: A data reuse analysis technique for efficient scratch-pad memory management. 15 - Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi:
Low test application time resource binding for behavioral synthesis. 16 - Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar:
A critical-path-aware partial gating approach for test power reduction. 17 - Irith Pomeranz, Sudhakar M. Reddy:
Forming N-detection test sets without test generation. 18 - Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung:
The exact channel density and compound design for generic universal switch blocks. 19
Volume 12, Number 3, August 2007
- Sung Kyu Lim, Massoud Pedram:
Introduction to special issue on demonstrable software systems and hardware platforms. 20:1-20:3 - Chia-Jui Hsu, Ming-Yung Ko, Shuvra S. Bhattacharyya, Suren Ramasubbu, José Luis Pino:
Efficient simulation of critical synchronous dataflow graphs. 21:1-21:28 - Fernando Herrera, Eugenio Villar:
A framework for heterogeneous specification and design of electronic embedded systems in SystemC. 22:1-22:31 - Hyung Gyu Lee, Naehyuck Chang, Ümit Y. Ogras, Radu Marculescu:
On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches. 23:1-23:20 - Soonhoi Ha, Sungchan Kim, Choonseung Lee, Youngmin Yi, Seongnam Kwon, Young-Pyo Joo:
PeaCE: A hardware-software codesign environment for multimedia embedded systems. 24:1-24:25 - David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida:
HW-SW emulation framework for temperature-aware design in MPSoCs. 26:1-26:26 - Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan:
Efficient power modeling and software thermal sensing for runtime temperature monitoring. 25:1-25:29 - Po-Kuan Huang, Soheil Ghiasi:
Efficient and scalable compiler-directed energy optimization for realtime applications. 27:1-27:16 - Yiyu Shi, Paul Mesa, Hao Yu, Lei He:
Circuit-simulated obstacle-aware Steiner routing. 28:1-28:18 - Lakshmi N. Chakrapani, Pinar Korkmaz, Bilge Saglam Akgul, Krishna V. Palem:
Probabilistic system-on-a-chip architectures. 29:1-29:28 - Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang:
A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current. 30:1-30:25 - Tathagato Rai Dastidar, P. P. Chakrabarti:
A verification system for transient response of analog circuits. 31:1-31:39 - Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Postplacement rewiring by exhaustive search for functional symmetries. 32:1-32:21 - Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch:
EWD: A metamodeling driven customizable multi-MoC system modeling framework. 33:1-33:43 - Greg Stitt, Frank Vahid:
Binary synthesis. 34:1-34:30 - Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis:
Speedups in embedded systems with a high-performance coprocessor datapath. 35:1-35:22 - Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta:
Event propagation for accurate circuit delay calculation using SAT. 36:1-36:23
Volume 12, Number 4, September 2007
- Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Temporal floorplanning using the three-dimensional transitive closure subGraph. 37 - Jinfeng Liu, Pai H. Chou:
Idle energy minimization by mode sequence optimization. 38 - Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou:
Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling. 39 - Peter Vanbroekhoven, Gerda Janssens, Maurice Bruynooghe, Francky Catthoor:
A practical dynamic single assignment transformation. 40 - Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai:
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. 41 - Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Techniques for the synthesis of reversible Toffoli networks. 42 - Youcef Bouchebaba, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid, Bruno Lavigueur, Pierre G. Paulin:
MPSoC memory optimization using program transformation. 43 - Dipankar Das, P. P. Chakrabarti, Rajeev Kumar:
Functional verification of task partitioning for multiprocessor embedded systems. 44 - Shih-Hsu Huang, Yow-Tyng Nieh:
Clock skew scheduling with race conditions considered. 45 - Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner:
Exploring time/resource trade-offs by solving dual scheduling problems with the ant colony optimization. 46 - Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
Low-Power and testable circuit synthesis using Shannon decomposition. 47 - Christopher Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan:
ILP and heuristic techniques for system-level design on network processor architectures. 48 - Sivaram Gopalakrishnan, Priyank Kalla:
Optimization of polynomial datapaths using finite ring algebra. 49 - Qubo Hu, Per Gunnar Kjeldsberg, Arnout Vandecappelle, Martin Palkovic, Francky Catthoor:
Incremental hierarchical memory size estimation for steering of loop transformations. 50 - Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee:
Compilation for compact power-gating controls. 51 - Gang Chen, Xiaoyu Song, Feng Liu, QingPing Tan, Fei He:
A note on "a mapping algorithm for computer-assisted exploration in the design of embedded systems". 52
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