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ORCIDMicroprocessors and Microsystems, Volume 22
Volume 22, Number 1, June 1998
- J. Giridhar, K. M. M. Prabhu:
Implementation of MTD-WVD on a TMS320C30 DSP processor. 1-12 - R. D. L. Stout, Ad J. van de Goor, R. E. Wolff:
Automatic fault localization at chip level. 13-22 - Efraim Berkovich, Simon Y. Berkovich:
A combinatorial architecture for instruction-level parallelism. 23-31 - Jesung Kim, Sang Lyul Min, Chong-Sang Kim:
U-cache: A cost-effective solution to the virtual cache synonym problem. 33-40 - Thambipillai Srikanthan, Goh Wee Leng, S. K. Amarasinghe:
An OLE-based speech compression system for multimedia applications. 41-48 - Steven Wallace, Nader Bagherzadeh:
A scalable register file architecture for superscalar processors. 49-60
Volume 22, Number 2, June 1998
- Shipping Huang, Malcolm I. Heywood
, Rupert C. D. Young, Maria Farsari, Chris R. Chatwin:
Systems control for a micro-stereolithography prototype. 67-77 - Zoran Salcic, Chung-Ruey Lee:
K-FLIX - a framework for custom-configurable embedded Kalman filter microcomputers. 79-86 - Tony P. W. Price, David M. Howard, Andrew M. Tyrrell:
Stereo output transputer interface board. 87-101 - W. K. Chou:
New processing elements: Max and sum_max with applications. 103-110 - Sebastiano Aiello, Antonio Anzalone, Massimo Bartolucci, Giuseppe Cardella, Salvatore Cavallaro, Enrico De Filippo, Stefano Feminò, Mario Geraci, Francesco Giustolisi, Paolo Guazzoni, Carmelo Marcello Iacono-Manno, Gaetano Lanzalone, Gaetano Lanzanò, Salvatore Lo Nigro, Giorgio Manfredi, Angelo Pagano, Massimo Papa, Sara Pirrone, Giuseppe Politi, Francesco Porto, Francesca Rizzo, Salvatore Sambataro, Giacomo R. Sechi, Maria Leda Sperduto, Concetta Sutera, Luisa Zetta:
Comparing different architectures for real-time computing of special algorithms: A case study. 111-120 - Martin W. S. Macauley:
Interrupt latency in systems based on Intel 80×86 processors. 121-126
Volume 22, Numbers 3-4, August 1998
- Chris Dick, Fred Harris:
Virtual signal processors. 135-148 - Dirk Fimmel, Renate Merker:
Determination of processor allocation in the design of processor arrays. 149-155 - Abdel-Halim Smai, Lars-Erik Thorelli:
Supporting high priority traffic in wormhole networks. 157-164 - Zhiyuan Li, Jian Huang, Guohua Jin:
Page-mapping techniques to reduce cache conflicts on CC-NUMA multiprocessors. 165-174 - Amnon Barak, Avner Braverman:
Memory ushering in a scalable computing cluster. 175-182 - Jackie Silcock, Andrzej Goscinski:
The RHODOS DSM system. 183-196 - Tatsuhiro Tsuchiya, Tetsuya Osada, Tohru Kikuno:
Genetics-based multiprocessor scheduling using task duplication. 197-207 - Richard Wong, Rodney W. Topor, Hong Shen:
A parallel sort-balance mutual range-join algorithm on hypercube computers. 209-215
Volume 22, Number 5, September 1998
- John N. Lygouras, Konstantinos A. Lalakos, Philippos G. Tsalides:
THETIS: an underwater remotely operated vehicle for water pollution measurements. 227-237 - Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo:
High performance VLSI modules for division and square root. 239-246 - Alberto Bartoli, Gianluca Dini:
Mechanisms for application-level recoverable-persistence in a single address space. 247-261 - Ch. Krieger, Bedrich J. Hosticka, Th. Krupp, Manfred Hiller, Andrés Kecskeméthy:
A combined hardware/software approach for fast kinematic processing. 263-275
Volume 22, Number 6, November 1998
- Daniel Tabak:
Special issue on Instruction Level Parallelism (ILP). 291-292 - José González, Antonio González:
Data value speculation in superscalar processors. 293-301 - Rahul Sathe, Kai Wang, Manoj Franklin:
Techniques for performing highly accurate data value prediction. 303-313 - Freddy Gabbay, Avi Mendelson:
Improving achievable ILP through value prediction and program profiling. 315-332 - Narayan Ranganathan, Manoj Franklin:
The PEWs microarchitecture: reducing complexity through data-dependence based decentralization. 333-343
Volume 22, Number 7, January 1999
- Austin Underhill, Mohammed Atiquzzaman, John Ophel:
Performance of the Hough transform on a distributed memory multiprocessor. 355-362 - Peter Kok Keong Loh, Wentong Cai:
Effects of topology and buffering on a processor farm. 363-372 - Kimmo Kuusilinna, Timo Hämäläinen, Jukka Saarinen:
Field programmable gate array-based PCI interface for a coprocessor system. 373-388 - Germán Galeano Gil, Juan Antonio Gómez Pulido, Juan M. Sánchez-Pérez:
Tool for the analysis and memory-trace generation of DOS executable files. 389-393 - Schubert Foo, Chai Kiat Yeo, Siu Cheung Hui, D. H. Xue:
Design of an Internet fax and voice gateway. 395-402 - Gyungho Lee, Bland Quattlebaum, Sangyeun Cho, Larry L. Kinney:
Design of a bus-based shared-memory multiprocessor DICE. 403-411 - Woon-Seng Gan, Yong Kim Chong, Meng Joo Er:
A low-cost digital signal processor-based ear-muff with adaptive active noise control. 413-422
Volume 22, Number 8, February 1999
- Alan Grigg, Neil C. Audsley:
Towards a scheduling and timing analysis solution for integrated modular avionic systems. 423-431 - Don C. Winter:
Open systems Ada technology demonstration program. 433-438 - M. W. Beranek, E. Y. Chan, H. E. Hager, Q. N. Le, J. S. Wilgus:
Emerging opportunities for applying COTS optoelectronics in avionics fiber-optic networks. 439-451 - M. J. Harris:
ATM for legacy aircraft avionics. 453-463 - Alexander A. Cameron:
Visor projected helmet mounted displays technology and applications. 465-475 - C. S. Dyer, P. R. Truscott:
Cosmic radiation effects on avionics. 477-483 - Robert Sternowski:
Digital signal processing (DSP) radios: trends, benefits and challenges. 485-491 - Roger Shaw:
Ground zero zero: flying into the next millennium with embedded systems. 493-500
Volume 22, Number 9, March 1999
- Veselko Gustin:
An FPGA extension to ALU functions. 501-508 - Mohamed Ould-Khaoua:
Message latency in the 2-dimensional mesh with wormhole routing. 509-514 - S. Kalaiselvi, V. Rajaraman:
A checkpointing algorithm for an SCI based distributed shared memory system. 515-522 - Jaime C. Fonseca, João Luiz Afonso, Júlio S. Martins, Carlos Couto:
Fuzzy logic speed control of an induction motor. 523-534 - C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal:
A functional-level testability measure for register-level circuits and its estimation. 535-542 - Zoran Salcic, Man Sum Cheng:
RAPROS - A rapid prototyping system and run-time environment for PC-based hardware/software applications. 543-552 - F. Thomas, J. K. Kishore, K. M. Bharadwaj, M. M. Nayak, V. K. Agrawal:
Design and implementation of a wheel speed measurement circuit using field programmable gate arrays in a spacecraft. 553-560 - Seongwoo Kim, Arun K. Somani:
An adaptive write error detection technique in on-chip caches of multi-level caching systems. 561-570 - Václav Dvorák:
Advanced Computer Architectures - a Design Space Approach, D. Sima, T. Fountain, P. Kacsuk (Eds.), Addison-Wesley Longman Ltd., 1997, ISBN 0-201-42291-3. 571-572 - J. Giridhar, K. M. M. Prabhu:
Erratum to "Implementation of MTD-WVD on a TMS320C30 DSP processor": [J. Microprocessors Microsyst. 22 (1998) 1-12]. 573
Volume 22, Number 10, May 1999
- Shiduan Cheng, Junliang Chen:
Guest editorial. 577-578 - Shuo-Yen Robert Li, W. Lam:
ATM switching by divide-and-conquer interconnection of partial sorters. 579-587 - Koenraad Laevens:
A processor-sharing model for input-buffered ATM-switches in a correlated traffic environment. 589-596 - Xinyu Wang, James S. Meditch:
A predictive bandwidth management scheme and network architecture for real-time VBR traffic. 597-604 - K.-P. Ho:
Broadcast digital subscriber lines using discrete multitone for broadband access. 605-610 - H. Gung, L. Zhenming:
Analysis of multiple sources delayed releasing SVCC based data communications over ATM. 611-618
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