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ORCIDVTS 2013: Berkeley, CA, USA
- 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-5542-1
- Mukesh Agrawal, Krishnendu Chakrabarty
:
Test-cost optimization and test-flow selection for 3D-stacked ICs. 1-6 - Koji Asami, Takashi Shimura, Toshiaki Kurihara:
Novel estimation method of EVM with channel correction for linear impairments in multi-standard RF transceivers. 1-6 - Ameya Chaudhari, Junyoung Park, Jacob A. Abraham:
A framework for low overhead hardware based runtime control flow error detection and recovery. 1-6 - Saman Kiamehr, Mojtaba Ebrahimi, Farshad Firouzi, Mehdi Baradaran Tahoori:
Chip-level modeling and analysis of electrical masking of soft errors. 1-6 - Kai Hu, Tsung-Yi Ho, Krishnendu Chakrabarty:
Testing of flow-based microfluidic biochips. 1-6 - Sachin Dileep Dasnurkar, Animesh Datta, Mohamed H. Abu-Rahma, Hieu Nguyen, Martin Villafana, Hadi Rasouli, Sean Tamjidi, Ming Cai, Samit Sengupta, P. R. Chidambaram, Raghavan Thirumala, Nikhil Kulkarni, Prasanna Seeram, Prasad Bhadri, Prayag Patel, Sei Seung Yoon, Esin Terzioglu:
Experiments and analysis to characterize logic state retention limitations in 28nm process node. 1-6 - Jin-Fu Li, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai:
Special session 4C: Hot topic 3D-IC design and test. 1 - Jae Woong Jeong, Sule Ozev, Shreyas Sen, T. M. Mak:
Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmitters. 1-6 - Chen-Yong Cher, Yiorgos Makris, C. Thibeault, Alan J. Drake:
Innovative practices session 7C: Self-calibration & trimming. 1 - Saghir A. Shaikh:
Innovative practices session 3C: Harnessing the challenges of testability and debug of high speed I/Os. 1 - Sreenivaas S. Muthyala, Nur A. Touba:
SOC test compression scheme using sequential linear decompressors with retained free variables. 1-6 - Brandon Noia, Krishnendu Chakrabarty:
Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs. 1-6 - Bo Yao, Arani Sinha, Irith Pomeranz:
Path selection based on static timing analysis considering input necessary assignments. 1-6 - Helia Naeimi, Suriya Natarajan, Kushagra Vaid, Prabhakar Kudva, Mahesh Natu:
Innovative practices session 5C: Cloud atlas - Unreliability through massive connectivity. 1 - Fayrouz Haddad, Wenceslas Rahajandraibe, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal:
On the investigation of built-in tuning of RF receivers using on-chip polyphase filters. 1-6 - Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret:
Reduced code linearity testing of pipeline adcs in the presence of noise. 1-6 - Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
A built-in scheme for testing and repairing voltage regulators of low-power srams. 1-6 - Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. 1-6 - Aitzan Sari, Mihalis Psarakis, Dimitris Gizopoulos:
Combining checkpointing and scrubbing in FPGA-based real-time systems. 1-6 - Bozena Kaminska, Bernard Courtois, Massimo Alioto:
New topic session 7B: Challenges and directions for ultra-low voltage VLSI circuits and systems: CMOS and beyond. 1 - Sen-Wen Hsiao, Nicholas Tzou, Abhijit Chatterjee:
A programmable BIST design for PLL static phase offset estimation and clock duty cycle detection. 1-6 - Thomas Moon, Hyun Woo Choi, Abhijit Chatterjee:
Low-cost multi-channel testing of periodic signals using monobit receivers and incoherent subsampling. 1-6 - Samed Maltabas, Osman Kubilay Ekekon, Kemal Kulovic, Anne Meixner, Martin Margala:
An IDDQ BIST approach to characterize phase-locked loop parameters. 1-6 - Keith A. Jenkins, Phillip J. Restle, P. Z. Wang, D. Hogenmiller, David W. Boerstler, Thomas J. Bucelot:
On-chip circuit for measuring multi-GHz clock signal waveforms. 1-4 - Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin:
3D-IC interconnect test, diagnosis, and repair. 1-6 - Michele Portolan, Michail Maniatakos:
Special session 8A: E.J. McCluskey doctoral thesis award semi-final - presentations. 1 - Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
An effective solution for building memory BIST infrastructure based on fault periodicity. 1-6 - Yue Gao, Yang Zhang, Da Cheng, Melvin A. Breuer:
Trading off area, yield and performance via hybrid redundancy in multi-core architectures. 1-6 - Xuehui Zhang, Kan Xiao, Mohammad Tehranipoor, Jeyavijayan Rajendran, Ramesh Karri:
A study on the effectiveness of Trojan detection techniques using a red team blue team approach. 1-3 - Chen-Wei Lin, Chin-Yuan Huang, Mango Chia-Tso Chao:
Testing of a low-VMIN data-aware dynamic-supply 8T SRAM. 1-6 - Chih-Sheng Hou, Jin-Fu Li:
Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs. 1-6 - Erik Larsson:
Special session 9B: Embedded tutorial embedded DfT instrumentation: Design, access, retargeting and case studies. 1-2 - Michael Patterson, Aaron Mills, Ryan A. Scheel, Julie Tillman, Evan Dye, Joseph Zambreno:
A multi-faceted approach to FPGA-based Trojan circuit detection. 1-4 - P. Pant, M. Amodeo, Sujal Vora, Jonathon E. Colburn:
Innovative practices session 10C: Delay test. 1 - Takahiro J. Yamaguchi, Jacob A. Abraham, Gordon W. Roberts, Suriyaprakash Natarajan, Dennis J. Ciplickas:
Special session 12B: Panel post-silicon validation & test in huge variance era. 1 - Yu Huang, Xiaoxin Fan, Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Brady Benware, Sudhakar M. Reddy:
Distributed dynamic partitioning based diagnosis of scan chain. 1-6 - Michele Portolan, Michail Maniatakos:
Special session 3B: E.J. McCluskey Doctoral Thesis Award semi-final - Posters. 1 - Chen-Yong Cher, Mohan J. Kumar:
Innovative practices session 11C: Resilience. 1 - Hao-Wen Hsu, Shih-Hua Kuo, Wen-Hsiang Chang, Shi-Hao Chen, Ming-Tung Chang, Mango Chia-Tso Chao:
Testing retention flip-flops in power-gated designs. 1-6 - Bozena Kaminska, Bernard Courtois, Soha Hassoun:
New topic session 2B: Why (Re-)Designing Biology is ∗Slightly∗ more challenging than designing electronics. 1 - Jonathon E. Colburn, Kun Young Chung, Haluk Konuk, Y. Dong:
Innovative practices session 6C: Latest practices in test compression. 1 - Rashid Rashidzadeh:
Contactless test access mechanism for TSV based 3D ICs. 1-6 - David Hély, Julien Martin, Gerson Dario Piraquive Triana, Simon Piroux Mounier, Elie Riviere, Thibault Sahuc, Jeremy Savonet, Laura Soundararadjou:
Experiences in side channel and testing based Hardware Trojan detection. 1-4 - Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal:
Finding best voltage and frequency to shorten power-constrained test time. 1-6 - Yuntan Fang, Huawei Li, Xiaowei Li:
RSAK: Random stream attack for phase change memory in video applications. 1-6 - Panagiota Papavramidou, Michael Nicolaidis:
An iterative diagnosis approach for ECC-based memory repair. 1-6 - Nagib Hakim, Charles Meissner:
Innovative practices session 1C: Post-silicon validation. 1-2 - Peter Wohl, John A. Waicukauski:
Improving test generation by use of majority gates. 1-6 - Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet:
Defect-oriented non-intrusive RF test using on-chip temperature sensors. 1-6 - Anshuman Chandra:
Special session 11B: Hot topic on-chip clocking - Industrial trends. 1 - Chen-Wei Lin, Mango Chia-Tso Chao, Chih-Chieh Hsu:
Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs. 1-6 - Andreas Riefert, Jörg Müller, Matthias Sauer, Wolfram Burgard, Bernd Becker:
Identification of critical variables using an FPGA-based fault injection framework. 1-6 - B. Seshadri, Bruce Cory, S. Mitra:
Innovative practices session 9C: Yield improvement: Challenges and directions. 1 - Ilia Polian, Mohammad Tehranipoor:
Special session 12A: Hot topic counterfeit IC identification: How can test help? 1 - Harm C. M. Bossers, Johann L. Hurink, Gerard J. M. Smit:
Selection of tests for outlier detection. 1-6 - Baris Arslan, Alex Orailoglu:
Tracing the best test mix through multi-variate quality tracking. 1-6 - Christopher Bell, Matthew Lewandowski, Srinivas Katkoori:
A multi-parameter functional side-channel analysis method for hardware trust verification. 1-4 - Adrian Evans, Michael Nicolaidis, Rob Aitken, Burcin Aktan, Olivier Lauzeral:
Hot topic session 4A: Reliability analysis of complex digital systems. 1 - Manuel d'Abreu, Amitava Mazumdar:
Special session 8B: Embedded tutorial challenges in SSD. 1 - Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia:
Special session 4B: Elevator talks. 1 - Tengteng Zhang, Duncan M. Hank Walker:
Power supply noise control in pseudo functional test. 1-6 - Alodeep Sanyal, Yervant Zorian:
Special session 12C: Town-hall meeting "young professionals in test". 1 - Barry John Muldrey, Sabyasachi Deyati, Michael Giardino, Abhijit Chatterjee:
RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuning. 1-6 - Sushmita Kadiyala Rao, Ryan W. Robucci, Chintan Patel:
Scalable dynamic technique for accurately predicting power-supply noise and path delay. 1-6 - Charutosh Dixit, Ramesh C. Tekumalla, Sreejit Chakravarty, Manuel d'Abreu, Zhuoyu Bao, Concetta Riccobene:
Innovative practices session 2C: Memory test. 1 - Prasanjeet Das, Sandeep K. Gupta:
Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning. 1-6 - Kihyuk Han, Joon-Sung Yang, Jacob A. Abraham:
Enhanced algorithm of combining trace and scan signals in post-silicon validation. 1-6 - Raymond Paseman, Alex Orailoglu:
Towards a cost-effective hardware trojan detection methodology. 1-3
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