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ORCIDNANOARCH 2014: Paris, France
- Jacques-Olivier Klein, Csaba Andras Moritz, Sorin Cotofana:
IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014, Paris, France, July 8-10, 2014. IEEE Computer Society/ACM 2014, ISBN 978-1-4799-6383-6 - Pilin Junsangsri, Fabrizio Lombardi, Jie Han:
A memristor-based TCAM (Ternary Content Addressable Memory) cell. 1-6 - Djaafar Chabi, Zhaohao Wang, Weisheng Zhao, Jacques-Olivier Klein
:
On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron. 7-12 - David Roclin, Olivier Bichler, Christian Gamrat, Jacques-Olivier Klein:
Sneak paths effects in CBRAM memristive devices arrays for spiking neural networks. 13-18 - Walt Woods, Jens Bürger, Christof Teuscher:
On the influence of synaptic weight states in a locally competitive algorithm for memristive hardware. 19-24 - Odysseas Zografos, Praveen Raghavan, Luca Gaetano Amarù, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Diederik Verkest, Aaron Thean:
System-level assessment and area evaluation of Spin Wave logic circuits. 25-30 - Kejie Huang, Rong Zhao, Yong Lian:
STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing. 31-36 - Mircea R. Stan, Mehdi Kabir, Stuart A. Wolf, Jiwei Lu:
Spin torque nano oscillators as key building blocks for the Systems-on-Chip of the future. 37-38 - Jinghua Yang, Niranjan Kulkarni, Shimeng Yu, Sarma B. K. Vrudhula:
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. 39-44 - Pilin Junsangsri, Fabrizio Lombardi, Jie Han:
HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design. 45-50 - David B. Dgien, Poovaiah M. Palangappa, Nathan Altay Hunter, Jiayin Li, Kartik Mohanram:
Compression architecture for bit-write reduction in non-volatile memory technologies. 51-56 - Mostafizur Rahman, Mingyu Li, Jiajun Shi, Santosh Khasanvis, Csaba Andras Moritz:
A new Tunnel-FET based RAM concept for ultra-low power applications. 57-58 - Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu:
Analog-to-stochastic converter using magnetic-tunnel junction devices. 59-64 - Davide Giri, Marco Vacca, Giovanni Causapruno, Wenjing Rao, Mariagrazia Graziano, Maurizio Zamboni:
A standard cell approach for MagnetoElastic NML circuits. 65-70 - Nesrine Ben Romdhane, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Z. R. Wang, Dafine Ravelosona:
Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires. 71-76 - Nusrat Jahan Lisa, Hafiz Md. Hasan Babu:
Minimization of a reversible quantum 2n-to-n BCD priority encoder. 77-82 - Wanlong Chen, Xiao Yang, Frank Zhigang Wang:
Memristor content addressable memory. 83-87 - Magnus Själander, Nina Shariati Nilsson, Stefanos Kaxiras:
A tunable cache for approximate computing. 88-89 - David Colliaux, Pierre Bessière, Jacques Droulez:
Robust sequence storage in bistable oscillators. 90-91 - Melika Payvand, Justin Rofeh, Avantika Sodhi, Luke Theogarajan:
A CMOS-memristive self-learning neural network for pattern classification applications. 92-97 - Ravi Patel, Eby G. Friedman:
Sub-crosspoint RRAM decoding for improved area efficiency. 98-103 - Jens Bürger, Christof Teuscher:
Volatile memristive devices as short-term memory in a neuromorphic learning architecture. 104-109 - Nickvash Kani, Azad Naeemi:
Pipeline design in spintronic circuits. 110-115 - Alireza Goudarzi, Matthew R. Lakin, Darko Stefanovic, Christof Teuscher:
A model for variation- and fault-tolerant digital logic using self-assembled nanowire architectures. 116-121 - Nandakishor Yadav, Shikha Jain, Manisha Pattanaik, G. K. Sharma:
NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique. 122-128 - Ali Zahir, Syed Azhar Ali Zaidi, Azzurra Pulimeno, Mariagrazia Graziano, Danilo Demarchi, Guido Masera, Gianluca Piccinini:
Molecular transistor circuits: From device model to circuit simulation. 129-134 - Miguel Diez-Garcia, Adrien F. Vincent, Nicolas Izard, Damien Querlioz:
Monte Carlo simulations of carbon nanotube networks for optoelectronic applications. 135-136 - Jana Tittmann, Sascha Hermann, Stefan E. Schulz, Anibal Pacheco-Sanchez, Martin Claus, Michael Schröter:
Hysteresis-free carbon nanotube field-effect transistors without passivation. 137-138 - Honghui Sun, Liang Fang, Yao Wang, Yaqing Chi, Rulin Liu:
A low contact resistance graphene field effect transistor with single-layer-channel and multi-layer-contact. 139-144 - Sumit Dutta, Vladimir Stojanovic:
Floating-point unit design with nano-electro-mechanical (NEM) relays. 145-150 - Mihai Lefter, Marius Enachescu, George Razvan Voicu, Sorin Dan Cotofana:
Energy effective 3D stacked hybrid NEMFET-CMOS caches. 151-156 - Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Majid Yazdani, Giovanni De Micheli:
Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. 163-168 - Catherine Dezan, Sara Zermani:
Stochastic reliability evaluation of Sea-of-Tiles based on Double Gate controllable-polarity FETs. 169-170 - Santosh Khasanvis, Mostafizur Rahman, Sankara Narayanan Rajapandian, Csaba Andras Moritz:
Wave-based multi-valued computation framework. 171-176 - Alexander N. Tait, Paul R. Prucnal:
Applications of wavelength-fan-in for high-performance distributed processing systems. 177-178 - Ciprian Teodorov, Loïc Lagadec:
Virtual prototyping of R2D NASIC based FPGA. 179-180
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