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ORCID50th DAC 2013: Austin, TX, USA
- The 50th Annual Design Automation Conference 2013, DAC '13, Austin, TX, USA, May 29 - June 07, 2013. ACM 2013, ISBN 978-1-4503-2071-9
Emerging mapping and management algorithms for parallel embedded systems
- Amit Kumar Singh, Muhammad Shafique
, Akash Kumar, Jörg Henkel:
Mapping on multi/many-core systems: survey of current and emerging trends. 1:1-1:10 - Pietro Mercati, Andrea Bartolini, Francesco Paterna, Tajana Simunic Rosing, Luca Benini:
Workload and user experience-aware dynamic reliability management in multicore processors. 2:1-2:6 - Mohamed Benazouz, Alix Munier Kordon, Thomas Hujsa, Bruno Bodin:
Liveness evaluation of a cyclo-static DataFlow graph. 3:1-3:7
Lay it out, analog!
- Hsing-Chih Chang Chien, Hung-Chih Ou, Tung-Chieh Chen, Ta-Yu Kuan, Yao-Wen Chang:
Double patterning lithography-aware analog placement. 4:1-4:6 - Hung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang:
Simultaneous analog placement and routing with current flow and current density considerations. 5:1-5:6 - Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao:
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits. 6:1-6:6 - Beiye Liu, Miao Hu, Hai Li, Zhi-Hong Mao, Yiran Chen, Tingwen Huang, Wei Zhang:
Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine. 7:1-7:6
Designing and modeling biology continues: hurdles and progress
- Natasa Miskov-Zivanov, Diana Marculescu, James R. Faeder:
Dynamic behavior of cell signaling networks: model design and analysis automation. 8:1-8:6
Transformations in FPGA design and productivity
- Jason Cong, Bingjun Xiao:
Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance. 9:1-9:8 - Tzu-Hen Lin, Pritha Banerjee, Yao-Wen Chang:
An efficient and effective analytical placer for FPGAs. 10:1-10:6 - Alexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu, Jason Cong, Yun Liang:
Throughput-oriented kernel porting onto FPGAs. 11:1-11:10 - Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, Jason Cong:
Memory partitioning for multidimensional arrays in high-level synthesis. 12:1-12:8
Balancing security and utility in medical devices
- Masoud Rostami, Wayne P. Burleson, Farinaz Koushanfar, Ari Juels:
Balancing security and utility in medical devices? 13:1-13:6 - Meng Zhang, Anand Raghunathan, Niraj K. Jha:
Towards trustworthy medical devices and body area networks. 14:1-14:6 - Junfeng Fan, Oscar Reparaz, Vladimir Rozic, Ingrid Verbauwhede:
Low-energy encryption for medical devices: security adds an extra design dimension. 15:1-15:6
Teaching the old backend compiler dog new tricks
- Abbas Rahimi, Luca Benini, Rajesh K. Gupta:
Aging-aware compiler-directed VLIW assignment for GPGPU architectures. 16:1-16:6 - Muhammad Shafique, Semeen Rehman, Pau Vilimelis Aceituno, Jörg Henkel:
Exploiting program-level masking and error propagation for constrained reliability optimization. 17:1-17:9 - Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula:
REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs). 18:1-18:10 - Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei:
Polyhedral model based mapping optimization of loop nests for CGRAs. 19:1-19:8
Answers to some of your embedded system design questions
- Lingamneni Avinash, Arindam Basu, Christian C. Enz, Krishna V. Palem, Christian Piguet:
Improving energy gains of inexact DSP hardware through reciprocative error compensation. 20:1-20:8 - Harry Wagstaff, Miles Gould, Björn Franke, Nigel P. Topham:
Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description. 21:1-21:6 - Su Myat Min, Haris Javaid, Sri Parameswaran:
XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs. 22:1-22:10 - Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens:
Towards variation-aware system-level power estimation of DRAMs: an empirical approach. 23:1-23:8
Don't fret about your FinFet: physical design in 14nm and beyond
- Arindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava, Bhavana Ballal, Pablo Royer Del Bario, Rogier Baert, Kris Croes, Julien Ryckaert, Mustafa Badaroglu, Abdelkarim Mercha, Diederik Verkest:
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. 24:1-24:6 - Shao-Yun Fang, Iou-Jen Liu, Yao-Wen Chang:
Stitch-aware routing for multiple e-beam lithography. 25:1-25:6 - Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala:
Automatic design rule correction in presence of multiple grids and track patterns. 26:1-26:6 - Yuan-Kai Ho, Yao-Wen Chang:
Multiple chip planning for chip-interposer codesign. 27:1-27:6
Taming the beast: coping with imperfect design and silicon defects
- Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li:
GPU-based n-detect transition fault ATPG. 28:1-28:8 - Li Lei, Fei Xie, Kai Cong:
Post-silicon conformance checking with virtual prototypes. 29:1-29:6 - Feng Yuan, Yannan Liu, Wen-Ben Jone, Qiang Xu:
On testing timing-speculative circuits. 30:1-30:6 - Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
An ATE assisted DFD technique for volume diagnosis of scan chains. 31:1-31:6
The silicon flashlight: mapping the road to 6nm
- Asen Asenov, Craig Alexander, Craig Riddet, Ewan Towie:
Predicting future technology performance. 32:1-32:6 - Veit Kleeberger, Helmut E. Graeb, Ulf Schlichtmann:
Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies. 33:1-33:6 - Andrew B. Kahng:
The ITRS design technology and system drivers roadmap: process and status. 34:1-34:6
Better to be proactive or be a slacker in NoC design?
- Ahmed Abousamra, Alex K. Jones, Rami G. Melhem:
Proactive circuit allocation in multiplane NoCs. 35:1-35:10 - Asit K. Mishra, Onur Mutlu, Chita R. Das:
A heterogeneous multiple network-on-chip design: an application-aware approach. 36:1-36:10 - Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan, Yuan Xie:
Designing energy-efficient NoC for real-time embedded systems through slack optimization. 37:1-37:6 - Hang Lu, Guihai Yan, Yinhe Han, Binzhang Fu, Xiaowei Li:
RISO: relaxed network-on-chip isolation for cloud processors. 38:1-38:6 - Mohammad Fattah, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila:
Smart hill climbing for agile dynamic mapping in many-core systems. 39:1-39:6 - Dean Michael Ancajas, James McCabe Nickerson, Koushik Chakraborty, Sanghamitra Roy:
HCI-tolerant NoC router microarchitecture. 40:1-40:10
Off-the-shelf techniques for quantum and bio circuits
- Alireza Shafaei, Mehdi Saeedi, Massoud Pedram:
Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures. 41:1-41:6 - Mohammad Javad Dousti, Massoud Pedram:
LEQA: latency estimation for a quantum algorithm mapped to a quantum circuit fabric. 42:1-42:7 - Claudio Angione, Jole Costanza, Giovanni Carapezza, Pietro Liò, Giuseppe Nicosia:
Pareto epsilon-dominance and identifiable solutions for BioCAD modeling. 43:1-43:9 - Yan Luo, Krishnendu Chakrabarty, Tsung-Yi Ho:
Design of cyberphysical digital microfluidic biochips under completion-time uncertainties in fluidic operations. 44:1-44:7 - Mona Yousofshahi, Michael Orshansky, Kyongbum Lee, Soha Hassoun:
Gene modification identification under flux capacity uncertainty. 45:1-45:5 - Daniel T. Grissom, Philip Brisk:
A field-programmable pin-constrained digital microfluidic biochip. 46:1-46:9
Enlarging the universe: innovative exploration for RTL and high-level synthesis
- Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition. 47:1-47:6 - Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. 48:1-48:8 - Kuan-Hua Tu, Jie-Hong R. Jiang:
Synthesis of feedback decoders for initialized encoders. 49:1-49:6 - Hung-Yi Liu, Luca P. Carloni:
On learning-based methods for design-space exploration with high-level synthesis. 50:1-50:7 - Mythri Alle, Antoine Morvan, Steven Derrien:
Runtime dependency analysis for loop pipelining in high-level synthesis. 51:1-51:10 - Alessandro Antonio Nacci, Vincenzo Rana, Francesco Bruschi, Donatella Sciuto, Ivan Beretta, David Atienza:
A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices. 52:1-52:6
Emerging application-oriented, low-power techniques
- Zhenyu Sun, Wenqing Wu, Hai (Helen) Li:
Cross-layer racetrack memory design for ultra high density and low power consumption. 53:1-53:6 - Vasileios Karakostas, Sasa Tomic, Osman S. Unsal, Mario Nemirovsky, Adrián Cristal:
Improving the energy efficiency of hardware-assisted watchpoint systems. 54:1-54:6 - Naoya Onizawa, Warren J. Gross:
Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks. 55:1-55:6 - Debashis Banerjee, Shyam Kumar Devarakond, Shreyas Sen, Abhijit Chatterjee:
Real-time use-aware adaptive MIMO RF receiver systems for energy efficiency under BER constraints. 56:1-56:7 - Yukan Zhang, Yang Ge, Qinru Qiu:
Improving charging efficiency with workload scheduling in energy harvesting embedded systems. 57:1-57:8 - Stefan Schürmans, Diandian Zhang, Dominik Auras, Rainer Leupers, Gerd Ascheid, Xiaotao Chen, Lun Wang:
Creation of ESL power models for communication architectures using automatic calibration. 58:1-58:58
Huff and PUF
- Raj Chakraborty, Charles Lamech, Dhruva Acharyya, Jim Plusquellic:
A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique. 59:1-59:10 - Yu Zheng, Maryamsadat Hashemian, Swarup Bhunia:
RESP: a robust physical unclonable function retrofitted into embedded SRAM array. 60:1-60:9 - Jie Zhang, Feng Yuan, Lingxiao Wei, Zelong Sun, Qiang Xu:
VeriTrust: verification for hardware trust. 61:1-61:8 - Tuo Li, Muhammad Shafique, Jude Angelo Ambrose, Semeen Rehman, Jörg Henkel, Sri Parameswaran:
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors. 62:1-62:7
Secrets of analog verification
- Aadithya V. Karthik, Jaijeet S. Roychowdhury:
ABCD-L: approximating continuous linear systems using boolean models. 63:1-63:9 - Fa Wang, Wangyang Zhang, Shupeng Sun, Xin Li, Chenjie Gu:
Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data. 64:1-64:6 - Chenjie Gu, Eli Chiprout, Xin Li:
Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation. 65:1-65:7 - Honghuang Lin, Peng Li, Chris J. Myers:
Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis. 66:1-66:6
Litho is hot!
- Yen-Ting Yu, Geng-He Lin, Iris Hui-Ru Jiang, Charles C. Chiang:
Machine-learning-based hotspot detection using topological classification and critical feature extraction. 67:1-67:6 - Sheng-Yuan Lin, Jing-Yi Chen, Jin-Cheng Li, Wan-Yu Wen, Shih-Chieh Chang:
A novel fuzzy matching model for lithography hotspot detection. 68:1-68:6 - Jian Kuang, Evangeline F. Y. Young:
An efficient layout decomposition approach for triple patterning lithography. 69:1-69:6 - Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan:
E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system. 70:1-70:7
Understanding mother nature and taming its wrath
- Wangyang Zhang, Xin Li, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar:
Automatic clustering of wafer spatial signatures. 71:1-71:6 - Haralampos-G. D. Stratigopoulos, Pierre Faubet, Yoann Courant, Firas Mohamed:
Multidimensional analog test metrics estimation using extreme value theory and statistical blockade. 72:1-72:7 - Kapil Dev, Gary L. Woods, Sherief Reda:
High-throughput TSV testing and characterization for 3D integration using thermal mapping. 73:1-73:6 - Li Jiang, Fangming Ye, Qiang Xu, Krishnendu Chakrabarty, Bill Eklow:
On effective and efficient in-field TSV repair for stacked 3D ICs. 74:1-74:6
The future of operating systems for embedded systems and software (ESS)
- Jan S. Rellermeyer, Seong-Won Lee, Michael Kistler:
Cloud platforms and embedded computing: the operating systems of the future. 75:1-75:6 - Juan A. Colmenares, Gage Eads, Steven A. Hofmeyr, Sarah Bird, Miquel Moretó, David Chou, Brian Gluzman, Eric Roman, Davide B. Bartolini, Nitesh Mor, Krste Asanovic, John Kubiatowicz:
Tessellation: refactoring the OS around explicit resource containers with continuous adaptation. 76:1-76:10 - Davide B. Bartolini, Riccardo Cattaneo, Gianluca Durelli, Martina Maggio, Marco D. Santambrogio, Filippo Sironi:
The autonomic operating system research project: achievements and future directions. 77:1-77:10
Captcha the chip!
- Xinmu Wang, Wen Yueh, Debapriya Basu Roy, Seetharam Narasimhan, Yu Zheng, Saibal Mukhopadhyay, Debdeep Mukhopadhyay, Swarup Bhunia:
Role of power grid in side channel attack and power-grid-aware secure design. 78:1-78:9 - Xueyang Wang, Ramesh Karri:
NumChecker: detecting kernel control-flow modifying rootkits by using hardware performance counters. 79:1-79:7 - Harikrishnan Chandrikakutty, Deepak Unnikrishnan, Russell Tessier, Tilman Wolf:
High-performance hardware monitors to protect network processors from data plane attacks. 80:1-80:6 - Giovanni Agosta, Alessandro Barenghi, Massimo Maggi, Gerardo Pelosi:
Compiler-based side channel vulnerability analysis and optimized countermeasures application. 81:1-81:6
Multi challenges of embedded multi-processing
- Ying Zhang, Lu Peng, Xin Fu, Yue Hu:
Lighting the dark silicon by exploiting heterogeneity on future processors. 82:1-82:7 - Rafael Garibotti, Luciano Ost, Rémi Busseuil, Mamady kourouma, Chris Adeniyi-Jones, Gilles Sassatelli, Michel Robert:
Simultaneous multithreading support in embedded distributed memory MPSoCs. 83:1-83:7 - Bojan Maric, Jaume Abella, Mateo Valero:
APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation. 84:1-84:8 - Yuan-Cheng Lee, Chih-wen Hsueh:
An optimized page translation for mobile virtualization. 85:1-85:6
Accelerated simulation and verification for power grid and memory
- Zhuo Feng:
Scalable vectorless power grid current integrity verification. 86:1-86:8 - Xuanxing Xiong, Jia Wang:
Constraint abstraction for vectorless power grid verification. 87:1-87:6 - Vivek Mishra, Sachin S. Sapatnekar:
The impact of electromigration in copper interconnects on power grid integrity. 88:1-88:6 - Lengfei Han, Xueqian Zhao, Zhuo Feng:
TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations. 89:1-89:8
We're gonna route around the clock
- Juyeon Kim, Deokjin Joo, Taewhan Kim:
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem. 90:1-90:6 - Andrew B. Kahng, Seokhyeong Kang, Hyein Lee:
Smart non-default routing for clock power reduction. 91:1-91:7 - Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan:
Routing congestion estimation with real design constraints. 92:1-92:8 - Yuelin Du, Qiang Ma, Hua Song, James P. Shiely, Gerard Luk-Pat, Alexander Miloslavsky, Martin D. F. Wong:
Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography. 93:1-93:6
21st century digital design tools
- William J. Dally, Chris Malachowsky, Stephen W. Keckler:
21st century digital design tools. 94:1-94:6
Electronics and software on wheels: embedded systems design challenges for electric vehicles and the path ahead
- Martin Lukasiewycz, Sebastian Steinhorst, Sidharta Andalam, Florian Sagstetter, Peter Waszecki, Wanli Chang, Matthias Kauer, Philipp Mundhenk, Shanker Shreejith, Suhaib A. Fahmy, Samarjit Chakraborty:
System architecture and software design for electric vehicles. 95:1-95:6 - Dip Goswami, Martin Lukasiewycz, Matthias Kauer, Sebastian Steinhorst, Alejandro Masrur, Samarjit Chakraborty, S. Ramesh:
Model-based development and verification of control software for electric vehicles. 96:1-96:9 - Sangyoung Park, Younghyun Kim, Naehyuck Chang:
Hybrid energy storage systems and battery management for electric vehicles. 97:1-97:6 - Georg Georgakos, Ulf Schlichtmann, Reinhard Schneider, Samarjit Chakraborty:
Reliability challenges for electric vehicles: from devices to architecture and systems software. 98:1-98:9
Adventures in time and space: targeting resiliency
- Jörg Henkel, Lars Bauer, Nikil D. Dutt, Puneet Gupta, Sani R. Nassif, Muhammad Shafique, Mehdi Baradaran Tahoori, Norbert Wehn:
Reliable on-chip systems in the nano-era: lessons learnt and future trends. 99:1-99:10 - Mojtaba Ebrahimi, Hossein Asadi, Mehdi Baradaran Tahoori:
A layout-based approach for multiple event transient analysis. 100:1-100:6 - Hyungmin Cho, Shahrzad Mirkhani, Chen-Yong Cher, Jacob A. Abraham, Subhasish Mitra:
Quantitative evaluation of soft error injection techniques for robust system design. 101:1-101:10 - Koushik Chakraborty, Brennan Cozzens, Sanghamitra Roy, Dean Michael Ancajas:
Efficiently tolerating timing violations in pipelined microprocessors. 102:1-102:8 - Zhen Wang:
Hierarchical decoding of double error correcting codes for high speed reliable memories. 103:1-103:7
New frontiers in EDA: from beyond CMOS to more than Moore
- Young-Joon Lee, Daniel B. Limbrick, Sung Kyu Lim:
Power benefit study for ultra-high density transistor-level monolithic 3D ICs. 104:1-104:10 - Gage Hills, Jie Zhang, Charles Mackin, Max M. Shulaker, Hai Wei, H.-S. Philip Wong, Subhasish Mitra:
Rapid exploration of processing and design guidelines to overcome carbon nanotube variations. 105:1-105:10 - Shiliang Liu, György Csaba, Xiaobo Sharon Hu, Edit Varga, Michael T. Niemier, Gary H. Bernstein, Wolfgang Porod:
Minimum-energy state guided physical design for nanomagnet logic. 106:1-106:7 - Mrigank Sharad, Deliang Fan, Kaushik Roy:
Ultra low power associative computing with spin neurons and resistive crossbar memory. 107:1-107:6 - Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Understanding the trade-offs in multi-level cell ReRAM memory design. 108:1-108:6 - Amit Ranjan Trivedi, Sergio Carlo, Saibal Mukhopadhyay:
Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifier. 109:1-109:6
Novel application scenarios for DVFS techniques
- Andrea Calimera, Enrico Macii, Massimo Poncino:
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints. 110:1-110:6 - Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Adithya Parandhaman, Anand Raghunathan:
Relax-and-retime: a methodology for energy-efficient recovery based design. 111:1-111:6 - Rong Ye, Feng Yuan, Zelong Sun, Wen-Ben Jone, Qiang Xu:
Post-placement voltage island generation for timing-speculative circuits. 112:1-112:6 - Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Analysis and characterization of inherent application resilience for approximate computing. 113:1-113:9 - Xi Chen, Zheng Xu, Hyungjun Kim, Paul V. Gratz, Jiang Hu, Michael Kishinevsky, Ümit Y. Ogras, Raid Zuhair Ayoub:
Dynamic voltage and frequency scaling for shared resources in multicore processor designs. 114:1-114:7 - Amit Kumar Singh, Anup Das, Akash Kumar:
Energy optimization by exploiting execution slacks in streaming applications on multiprocessor systems. 115:1-115:7
Verification: from SystemC to the reality of silicon
- Hoang Minh Le, Daniel Große, Vladimir Herdt, Rolf Drechsler:
Verifying SystemC using an intermediate verification language and symbolic simulation. 116:1-116:6 - Zhenkun Yang, Sandip Ray, Kecheng Hao, Fei Xie:
Handling design and implementation optimizations in equivalence checking for behavioral synthesis. 117:1-117:6 - Cheng-Yin Wu, Chi-An Wu, Chien-Yu Lai, Chung-Yang (Ric) Huang:
A counterexample-guided interpolant generation algorithm for SAT-based model checking. 118:1-118:6 - Bo-Han Wu, Chung-Yang (Ric) Huang:
A robust constraint solving framework for multiple constraint sets in constrained random verification. 119:1-119:7 - Wen Chen, Li-C. Wang, Jay Bhadra, Magdy S. Abadir:
Simulation knowledge extraction and reuse in constrained random processor verification. 120:1-120:6 - Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici:
Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation. 121:1-121:6
The role of cascade, a cycle-based simulation infrastructure, in designing the anton special-purpose supercomputers
- J. P. Grossman, Brian Towles, Joseph A. Bank, David E. Shaw:
The role of cascade, a cycle-based simulation infrastructure, in designing the anton special-purpose supercomputers. 122:1-122:9
The future is here: live demos of the "next" transistor
- Pierre-Emmanuel Gaillardon, Michele De Marchi, Luca Gaetano Amarù, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
Towards structured ASICs using polarity-tunable Si nanowire transistors. 123:1-123:4 - Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra:
Sacha: the Stanford carbon nanotube controlled handshaking robot. 124:1-124:3 - Tsuyoshi Sekitani, Tomoyuki Yokota, Makoto Takamiya, Takayasu Sakurai, Takao Someya:
Electrical artificial skin using ultraflexible organic transistor. 125:1-125:3 - Olivier Goncalves, Guillaume Prenat, Gregory di Pendina, Bernard Dieny:
Non-volatile FPGAs based on spintronic devices. 126:1-126:3 - Hossein Fariborzi, Fred Chen, Rhesa Nathanael, I-Ru Chen, Louis Hutin, Rinus Lee, Tsu-Jae King Liu, Vladimir Stojanovic:
Relays do not leak: CMOS does. 127:1-127:4 - Edoardo Charbon, Francesco Regazzoni:
Single-photon image sensors. 128:1-128:4
System compilation for multi-cores: analysis and synthesis
- Jinwoo Kim, Hyunok Oh, Junchul Choi, Hyojin Ha, Soonhoi Ha:
A novel analytical method for worst case response time estimation of distributed embedded systems. 129:1-129:10 - Janmartin Jahn, Santiago Pagani, Sebastian Kobbe, Jian-Jia Chen, Jörg Henkel:
Optimizations for configuring and mapping software pipelines in many core systems. 130:1-130:8 - Wei Quan, Andy D. Pimentel:
A scenario-based run-time task mapping algorithm for MPSoCs. 131:1-131:6 - Prashant Agrawal, Praveen Raghavan, Matthias Hartmann, Namita Sharma, Liesbet Van der Perre, Francky Catthoor:
Early exploration for platform architecture instantiation with multi-mode application partitioning. 132:1-132:8
Embedded: when applications and architectures collide
- Khawar Shahzad, Ayesha Khalid, Zoltán Endre Rákossy, Goutam Paul, Anupam Chattopadhyay:
CoARX: a coprocessor for ARX-based cryptographic algorithms. 133:1-133:10 - Liang Tang, Jude Angelo Ambrose, Sri Parameswaran:
Reconfigurable pipelined coprocessor for multi-mode communication transmission. 134:1-134:8 - Mi Sun Park, Chuanjun Zhang, Michael DeBole, Srinidhi Kestur:
Accelerators for biologically-inspired attention and recognition. 135:1-135:6 - Armin Alaghi, Cheng Li, John P. Hayes:
Stochastic circuits for real-time image-processing applications. 136:1-136:6
SPICE up the analysis!!
- Ji-Eun Jang, Myeong-Jae Park, Jaeha Kim:
An event-driven simulation methodology for integrated switching power supplies in SystemVerilog. 137:1-137:7 - G. Peter Fang:
A new time-stepping method for circuit simulation. 138:1-138:10 - Zuochang Ye, Bichen Wu, Song Han, Yang Li:
Time-domain segmentation based massively parallel simulation for ADCs. 139:1-139:6 - Bangda Zhou, Haixin Liu, Dan Jiao:
A direct finite element solver of linear complexity for large-scale 3-D circuit extraction in multiple dielectrics. 140:1-140:6
FPGAs as general-purpose processors: progress and challenges
- Walid A. Najjar, Jason R. Villarreal:
FPGA code accelerators - the compiler perspective. 141:1-141:6
Keeping Austin weird DAC-style: wilder and crazier ideas
- Smita Krishnaswamy, Bernd Bodenmiller, Dana Pe'er:
Can CAD cure cancer? 142:1-142:2 - Martin Geier, Martin Becker, Daniel Yunge, Benedikt Dietrich, Reinhard Schneider, Dip Goswami, Samarjit Chakraborty:
Let's put the car in your phone! 143:1-143:2 - Sheng Wei, Miodrag Potkonjak:
The undetectable and unprovable hardware trojan horse. 144:1-144:2 - Swaroop Ghosh:
Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5watts of power. 145:1-145:2
Predicting the future: hiding the memory bottleneck with predictable caches and scratchpads
- Emilio Wuerges, Rômulo Silva de Oliveira, Luiz C. V. dos Santos:
Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching. 146:1-146:9 - Huping Ding, Yun Liang, Tulika Mitra:
Integrated instruction cache analysis and locking in multitasking real-time systems. 147:1-147:10 - Sidharta Andalam, Alain Girault, Roopak Sinha, Partha S. Roop, Jan Reineke:
Precise timing analysis for direct-mapped caches. 148:1-148:10 - Jing Lu, Ke Bai, Aviral Shrivastava:
SSDM: smart stack data management for software managed multicores (SMMs). 149:1-149:8
One small step for placement, one big leap for routability!
- Jin Hu, Myung-Chul Kim, Igor L. Markov:
Taming the complexity of coordinated place and route. 150:1-150:7 - Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang:
Routability-driven placement for hierarchical mixed-size circuit designs. 151:1-151:6 - Xu He, Tao Huang, Wing-Kai Chow, Jian Kuang, Ka-Chun Lam, Wenzan Cai, Evangeline F. Y. Young:
Ripple 2.0: high quality routability-driven placement via global router integration. 152:1-152:6 - Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li:
Optimization of placement solutions for routability. 153:1-153:9
From classical to novel EDA sytems
- Bailey Miller, Frank Vahid, Tony Givargis:
Exploration with upgradeable models using statistical methods for physical model emulation. 154:1-154:6 - Matthias Kauer, Swaminathan Naranayaswami, Sebastian Steinhorst, Martin Lukasiewycz, Samarjit Chakraborty, Lars Hedrich:
Modular system-level architecture for concurrent cell balancing. 155:1-155:10 - Nicola Bombieri, Hung-Yi Liu, Franco Fummi, Luca P. Carloni:
A method to abstract RTL IP blocks into C++ code and enable high-level synthesis. 156:1-156:9 - Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy:
DMR3D: dynamic memory relocation in 3D multicore systems. 157:1-157:9
Powering heterogeneous SoCs at the right place and right time
- David Flynn:
Power gating applied to MP-SoCs for standby-mode power management. 158:1-158:5 - Tanay Karnik, Mondira (Mandy) Deb Pant, Shekhar Borkar:
Power management and delivery for high-performance microprocessors. 159:1-159:3 - Benton H. Calhoun, Kyle Craig:
Flexible on-chip power delivery for energy efficient heterogeneous systems. 160:1-160:6 - Miguel Corbalan, Anup Keval, Thomas Toms, Durodami Lisk, Riko Radojcic, Matt Nowak:
Power and signal integrity challenges in 3D systems. 161:1-161:4
Age of flash
- Hung-Wei Tseng, Laura M. Grupp, Steven Swanson:
Underpowering NAND flash: profits and perils. 162:1-162:6 - Ming-Chang Yang, Yuan-Hao Chang, Che-Wei Tsao, Po-Chun Huang:
New ERA: new efficient reliability-aware wear leveling for endurance enhancement of flash storage devices. 163:1-163:6 - Chundong Wang, Weng-Fai Wong:
SAW: system-assisted wear leveling on the write endurance of NAND flash devices. 164:1-164:9 - Che-Wei Tsao, Yuan-Hao Chang, Ming-Chang Yang:
Performance enhancement of garbage collection for flash storage devices: an efficient victim block selection design. 165:1-165:6 - Ren-Shuo Liu, Chia-Lin Yang, Cheng-Hsuan Li, Geng-You Chen:
DuraCache: a durable SSD cache using MLC NAND flash. 166:1-166:6
Why does constraint-driven design matter for multicore embedded systems?
- Devendra Rai, Lars Schor, Nikolay Stoimenov, Lothar Thiele:
Distributed stable states for process networks: algorithm, analysis, and experiments on intel SCC. 167:1-167:10 - Iraklis Anagnostopoulos, Vasileios Tsoutsouras, Alexandros Bartzas, Dimitrios Soudris:
Distributed run-time resource management for malleable applications on many-core platforms. 168:1-168:6 - YoungHoon Jung, Jinhyung Park, Michele Petracca, Luca P. Carloni:
netShip: a networked virtual platform for large-scale heterogeneous distributed embedded systems. 169:1-169:10 - Jiali Teddy Zhai, Mohamed Bamakhrama, Todor P. Stefanov:
Exploiting just-enough parallelism when mapping streaming applications in hard real-time systems. 170:1-170:8 - Yang Xu, Bo Wang, Ralph Hasholzner, Rafael Rosales, Jürgen Teich:
On robust task-accurate performance estimation. 171:1-171:6 - Philip Axer, Rolf Ernst:
Stochastic response-time guarantee for non-preemptive, fixed-priority scheduling under errors. 172:1-172:7
System design with power and thermal constraints
- Yatish Turakhia, Bharathwaj Raghunathan, Siddharth Garg, Diana Marculescu:
HaDeS: architectural synthesis for <u>h</u>eterogeneous <u>d</u>ark <u>s</u>ilicon chip multi-processors. 173:1-173:7 - Thannirmalai Somu Muthukaruppan, Mihai Pricopi, Vanchinathan Venkataramani, Tulika Mitra, Sanjay Vishin:
Hierarchical power management for asymmetric multi-core in dark silicon era. 174:1-174:9 - Sai Manoj Pudukotai Dinakarrao, Kanwen Wang, Hao Yu:
Peak power reduction and workload balancing by space-time multiplexing based demand-supply matching for 3D thousand-core microprocessor. 175:1-175:6 - Xin Zhan, Sherief Reda:
Techniques for energy-efficient power budgeting in data centers. 176:1-176:7 - Rajib Nath, Raid Zuhair Ayoub, Tajana Simunic Rosing:
Temperature aware thread block scheduling in GPGPUs. 177:1-177:6 - Hossein Tajik, Houman Homayoun, Nikil D. Dutt:
VAWOM: temperature and process variation aware wearout management in 3D multicore architecture. 178:1-178:8
Got yield problems? Take a closer look at variability and reliability!
- Sergio Carlo, Wen Yueh, Saibal Mukhopadhyay:
On the potential of 3D integration of inductive DC-DC converter for high-performance power delivery. 179:1-179:8 - Taigon Song, Chang Liu, Yarui Peng, Sung Kyu Lim:
Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs. 180:1-180:7 - Yang Li, David Z. Pan:
An accurate semi-analytical framework for full-chip TSV-induced stress modeling. 181:1-181:8 - Vimitha A. Kuruvilla, Debjit Sinha, Jeff Piaget, Chandu Visweswariah, Nitin Chandrachoodan:
Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization. 182:1-182:7 - Feng Yuan, Qiang Xu:
InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits. 183:1-183:6 - Chi-En Daniel Yin, Gang Qu:
Improving PUF security with regression-based distiller. 184:1-184:6
On the convergence of mainstream and mission-critical markets
- Sylvain Girbal, Miquel Moretó, Arnaud Grasset, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Sami Yehia:
On the convergence of mainstream and mission-critical markets. 185:1-185:10
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