"An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration."

Masato Motomura et al. (1998)

> Home

Details and statistics

DOI: 10.1109/FPGA.1998.707909

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/fccm/MotomuraASYY98
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fccm/MotomuraASYY98
Masato Motomura, Yoshiharu Aimoto, Atsufkni Shibayama, Yoshikazu Yabe, Masakazu Yamashina:
An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration. FCCM 1998: 264-266

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.