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- affiliation: University of Southampton, School of Electronics and Computer Science, UK
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2020 – today
- 2024
[c87]Ahmet Cirakoglu, Alexander Serb, Mark Zwolinski, Themis Prodromakis:
Investigation of Single-Event Upsets in Radiation Hardened RRAM Memory Cells. NewCAS 2024: 158-162- [i6]Bing Xue, Mark Zwolinski:
Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core. CoRR abs/2405.12089 (2024) - [i5]Xiao Liu, Mark Zwolinski, Basel Halak:
SEA Cache: A Performance-Efficient Countermeasure for Contention-based Attacks. CoRR abs/2405.20027 (2024) - 2022
- [c86]Mark Zwolinski:
Session details: Session 4A: Testing, Reliability and Fault Tolerance. ACM Great Lakes Symposium on VLSI 2022 - [c85]Bing Xue, Mark Zwolinski
:
Using Formal Methods to Evaluate Hardware Reliability in the Presence of Soft Errors. PRIME 2022: 29-32 - [c84]Xiao Liu, Mark Zwolinski:
Mitigating Cache Contention-Based Attacks by Logical Associativity. PRIME 2022: 229-232 - 2021
- [j39]Mohd Syafiq Mispan, Basel Halak, Mark Zwolinski:
A Survey on the Susceptibility of PUFs to Invasive, Semi-Invasive and Noninvasive Attacks: Challenges and Opportunities for Future Directions. J. Circuits Syst. Comput. 30(11): 2130009:1-2130009:37 (2021) - [j38]Haider Muhi Abbas, Basel Halak, Mark Zwolinski:
Learning-based BTI stress estimation and mitigation in multi-core processor systems. Microprocess. Microsystems 81: 103713 (2021)
2010 – 2019
- 2019
- [j37]Ibrahim A. Bello, Basel Halak, Mohammed El-Hajjar, Mark Zwolinski:
VLSI Implementation of a Fully-Pipelined K-Best MIMO Detector with Successive Interference Cancellation. Circuits Syst. Signal Process. 38(10): 4739-4761 (2019) - [j36]Mohd Syafiq Mispan, Shengyu Duan, Basel Halak, Mark Zwolinski:
A reliable PUF in a dual function SRAM. Integr. 68: 12-21 (2019) - [j35]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c83]Miao Yu, Basel Halak, Mark Zwolinski:
Using Hardware Performance Counters to Detect Control Hijacking Attacks. IVSW 2019: 1-6 - [c82]Haibo Su, Basel Halak, Mark Zwolinski:
Two-Stage Architectures for Resilient Lightweight PUFs. IVSW 2019: 19-24 - 2018
- [j34]Gaole Sai, Basel Halak, Mark Zwolinski:
Multi-Path Aging Sensor for Cost-Efficient Delay Fault Prediction. IEEE Trans. Circuits Syst. II Express Briefs 65-II(4): 491-495 (2018) - [j33]Shengyu Duan, Mark Zwolinski, Basel Halak:
Lifetime Reliability-Aware Digital Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2205-2216 (2018) - [c81]Shengyu Duan, Basel Halak, Mark Zwolinski:
Cell Flipping with Distributed Refresh for Cache Ageing Minimization. ATS 2018: 98-103 - [c80]Mohd Syafiq Mispan, Haibo Su, Mark Zwolinski, Basel Halak:
Cost-efficient design for modeling attacks resistant PUFs. DATE 2018: 467-472 - [c79]Lai Leng Woo, Mark Zwolinski, Basel Halak:
Early detection of system-level anomalous behaviour using hardware performance counters. DATE 2018: 485-490 - [c78]Sonal Yadav, Vijay Laxmi, Hemangee K. Kapoor, Manoj Singh Gaur, Mark Zwolinski:
A Power Efficient Crossbar Arbitration in Multi-NoC for Multicast and Broadcast Traffic. iSES 2018: 243-248 - [c77]Haibo Su, Mark Zwolinski, Basel Halak:
A Machine Learning Attacks Resistant Two Stage Physical Unclonable Functions Design. IVSW 2018: 52-55 - [c76]Mohd Syafiq Mispan, Shengyu Duan, Basel Halak, Mark Zwolinski:
A Reliable PUF in a Dual Function SRAM. PATMOS 2018: 76-81 - [c75]Ibrahim A. Bello, Basel Halak, Mohammed El-Hajjar, Mark Zwolinski:
Hardware Implementation of a Low-Power K-Best MIMO Detector Based on a Hybrid Merge Network. PATMOS 2018: 191-197 - 2017
- [j32]Haider Muhi Abbas, Basel Halak, Mark Zwolinski:
BTI mitigation by anti-ageing software patterns. Microelectron. Reliab. 79: 79-90 (2017) - [c74]Enrico Fraccaroli, Francesco Stefanni, Franco Fummi, Mark Zwolinski:
Fault analysis in analog circuits through language manipulation and abstraction. FDL 2017: 1-7 - [c73]Enrico Fraccaroli, Francesco Stefanni, Franco Fummi, Mark Zwolinski:
Fault Analysis in Analog Circuits Through Language Manipulation and Abstraction. FDL (Selected Papers) 2017: 89-105 - [c72]Gaole Sai, Basel Halak, Mark Zwolinski:
A cost-efficient delay-fault monitor. ISCAS 2017: 1-4 - [c71]Mohd Syafiq Mispan, Basel Halak, Mark Zwolinski:
Lightweight obfuscation techniques for modeling attacks resistant PUFs. IVSW 2017: 19-24 - [c70]Elena Lai Leng Woo, Mark Zwolinski, Basel Halak:
Hardware performance counters for system reliability monitoring. IVSW 2017: 76-81 - [c69]Shengyu Duan, Basel Halak, Mark Zwolinski:
An ageing-aware digital synthesis approach. SMACD 2017: 1-4 - 2016
- [j31]Anirban Sengupta, Saraju P. Mohanty, Fabrizio Lombardi, Mark Zwolinski:
IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices. IEEE Access 4: 2976-2980 (2016) - [j30]Ibrahim A. Bello, Basel Halak, Mohammed El-Hajjar, Mark Zwolinski:
A Survey of VLSI Implementations of Tree Search Algorithms for MIMO Detection. Circuits Syst. Signal Process. 35(10): 3644-3674 (2016) - [j29]Mark Zwolinski, Manoj Singh Gaur, Vijay Laxmi, Usha Sandeep Mehta:
Guest Editorial. IET Comput. Digit. Tech. 10(5): 203-204 (2016) - [j28]Niyati Gupta, Ashish Sharma, Vijay Laxmi, Manoj Singh Gaur, Mark Zwolinski, Rimpy Bishnoi:
σ n LBDR: generic congestion handling routing implementation for two-dimensional mesh network-on-chip. IET Comput. Digit. Tech. 10(5): 226-232 (2016) - [j27]Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, Mark Zwolinski:
Resilient routing implementation in 2D mesh NoC. Microelectron. Reliab. 56: 189-201 (2016) - [j26]Yang Lin, Mark Zwolinski, Basel Halak:
A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1688-1701 (2016) - [c68]Shengyu Duan, Basel Halak, Rick Wong, Mark Zwolinski:
NBTI Lifetime Evaluation and Extension in Instruction Caches. ERMAVSS@DATE 2016: 9-12 - [c67]Illani Mohd Nawi, Basel Halak, Mark Zwolinski:
Ageing Impact on a High Speed Voltage Comparator with Hysteresis. ERMAVSS@DATE 2016: 25-29 - [c66]Haider Abbas, Mark Zwolinski, Basel Halak:
Static Aging Analysis Using 3-Dimensional Delay Library. ERMAVSS@DATE 2016: 34-37 - [c65]Illani Mohd Nawi, Basel Halak, Mark Zwolinski:
The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparator. ETS 2016: 1-2 - [c64]Mark Zwolinski, Wolfgang Kunz, Kjetil Svarstad, Andrew D. Brown:
The European Masters in Embedded Computing Systems (EMECS). EWME 2016: 1-6 - [c63]Aliasghar Makhlooghpour, Hamid Soleimani, Arash Ahmadi, Mark Zwolinski, Mehrdad Saif:
High accuracy implementation of Adaptive Exponential integrated and fire neuron model. IJCNN 2016: 192-197 - [c62]Mohd Syafiq Mispan, Basel Halak, Mark Zwolinski:
NBTI aging evaluation of PUF-based differential architectures. IOLTS 2016: 103-108 - [c61]Basel Halak, Mark Zwolinski, Mohd Syafiq Mispan:
Overview of PUF-based hardware security solutions for the internet of things. MWSCAS 2016: 1-4 - [c60]Radi Husin Bin Ramlee, Mark Zwolinski:
Using Iddt current degradation to monitor ageing in CMOS circuits. PATMOS 2016: 200-204 - 2015
- [j25]Tarek Nechma, Mark Zwolinski:
Parallel Sparse Matrix Solution for Circuit Simulation on FPGAs. IEEE Trans. Computers 64(4): 1090-1103 (2015) - [j24]Mohamed Tagelsir Mohammadat, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin, Mark Zwolinski:
Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 580-583 (2015) - [c59]Sara Vinco, Michele Lora, Mark Zwolinski:
Conservative behavioural modelling in systemc-AMS. FDL 2015: 65-72 - [c58]Ibrahim A. Bello, Basel Halak, Mohammed El-Hajjar, Mark Zwolinski:
VLSI implementation of a scalable K-best MIMO detector. ISCIT 2015: 281-286 - [c57]Manoj Singh Gaur, Vijay Laxmi, Mark Zwolinski, Manoj Kumar, Niyati Gupta, Ashish Sharma:
Network-on-chip: Current issues and challenges. VDAT 2015: 1-3 - [c56]Niyati Gupta, Manoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Mark Zwolinski:
σLBDR: Congestion-aware logic based distributed routing for 2D NoC. VDAT 2015: 1-6 - [c55]Ashish Sharma, Prachi Upadhyay, Ruby Ansar, Vijay Laxmi, Lava Bhargava, Manoj Singh Gaur, Mark Zwolinski:
A framework for thermal aware reliability estimation in 2D NoC. VDAT 2015: 1-6 - [c54]Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, Radi Husin Bin Ramlee, Mark Zwolinski:
CERI: Cost-Effective Routing Implementation Technique for Network-on-Chip. VLSID 2015: 59-64 - [i4]Anton Kulakov, Mark Zwolinski, Jeffrey S. Reeve:
Fault Tolerance in Distributed Neural Computing. CoRR abs/1509.09199 (2015) - [i3]Massoud Mokhtarpour Ghahroodi, Mark Zwolinski:
In-Field Logic Repair of Deep Sub-Micron CMOS Processors. CoRR abs/1509.09249 (2015) - [i2]Mohd Azman Abdul Latif, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin, Mark Zwolinski:
Implications of Burn-In Stress on NBTI Degradation. CoRR abs/1510.01370 (2015) - 2014
- [j23]Michael Merrett, Mark Zwolinski:
Monte Carlo Static Timing Analysis with statistical sampling. Microelectron. Reliab. 54(2): 464-474 (2014) - [j22]Mohamed Tagelsir Mohammadat, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin, Mark Zwolinski:
Multivoltage Aware Resistive Open Fault Model. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 220-231 (2014) - [c53]Yang Lin, Mark Zwolinski, Basel Halak:
A low-cost radiation hardened flip-flop. DATE 2014: 1-6 - [c52]Ji Qi, Mark Zwolinski:
Efficient simulation and modelling of non-rectangular NoC topologies. DATE 2014: 1-4 - [c51]Manoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Masoud Daneshtalab, Masoumeh Ebrahimi, Mark Zwolinski:
Fault tolerant and highly adaptive routing for 2D NoCs. DFT 2014: 104-109 - [c50]Manoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Masoud Daneshtalab, Seok-Bum Ko, Mark Zwolinski:
Highly adaptive and congestion-aware routing for 3D NoCs. ACM Great Lakes Symposium on VLSI 2014: 97-98 - [c49]Yang Lin, Mark Zwolinski:
A cost-efficient self-checking register architecture for radiation hardened designs. ISCAS 2014: 149-152 - [c48]Manoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Masoud Daneshtalab, Pankaj Kumar Srivastava, Seok-Bum Ko, Mark Zwolinski:
A novel non-minimal/minimal turn model for highly adaptive routing in 2D NoCs. NOCS 2014: 184-185 - [c47]Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, Radi Husin Bin Ramlee, Mark Zwolinski:
Fault tolerant routing implementation mechanism for irregular 2D mesh NoCs. NORCHIP 2014: 1-4 - [c46]Manoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Masoud Daneshtalab, Mark Zwolinski:
A novel non-minimal turn model for highly adaptive routing in 2D NoCs. VLSI-SoC 2014: 1-6 - [c45]Manoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Seok-Bum Ko, Mark Zwolinski:
CARM: Congestion Adaptive Routing Method for On Chip Networks. VLSID 2014: 240-245 - 2013
- [j21]Miona Andrejevic Stosovic, Miljana Milic, Mark Zwolinski, Vanco B. Litovski:
Oscillation-based analog diagnosis using artificial neural networks based inference mechanism. Comput. Electr. Eng. 39(2): 190-201 (2013) - [j20]Liang Li, Robert G. Maunder, Bashir M. Al-Hashimi, Mark Zwolinski, Lajos Hanzo:
Energy-Conscious Turbo Decoder Design: A Joint Signal Processing and Transmit Energy Reduction Approach. IEEE Trans. Veh. Technol. 62(8): 3627-3638 (2013) - [c44]Cliff C. N. Sze, Laleh Behjat, Nikhil Jayakumar, Atul Walimbe, Gregory Ford, Mark Zwolinski, Harish Dangat, Giriraj Kakol:
ISPD 2013 expert designer/user session (eds). ISPD 2013: 137 - [c43]Kai Chi Alex Lam, Mark Zwolinski:
Circuit Transient Analysis Using State Space Equations. VDAT 2013: 330-336 - [e1]Manoj Singh Gaur, Mark Zwolinski, Vijay Laxmi, Dharmendar Boolchandani, Virendra Singh, Adit D. Singh:
VLSI Design and Test, 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Revised Selected Papers. Communications in Computer and Information Science 382, Springer 2013, ISBN 978-3-642-42023-8 [contents] - 2012
- [c42]Yang Lin, Mark Zwolinski:
SETTOFF: A fault tolerant flip-flop for building Cost-efficient Reliable Systems. IOLTS 2012: 7-12 - [c41]Hamid Soleimani, Arash Ahmadi, Mohammad Bavandpour, Amirali Amirsoleimani, Mark Zwolinski:
A Large Scale Digital Simulation of Spiking Neural Networks (SNN) on Fast SystemC Simulator. UKSim 2012: 25-30 - 2011
- [j19]Arash Ahmadi, Mark Zwolinski:
Fixed-point multiplication: A probabilistic bit-pattern view. Microelectron. Reliab. 51(4): 790-796 (2011) - [j18]Arash Ahmadi, Eduardo Mangieri, Koushik Maharatna, Srinandan Dasmahapatra, Mark Zwolinski:
On the VLSI Implementation of Adaptive-Frequency Hopf Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(5): 1076-1088 (2011) - [c40]Massoud Mokhtarpour Ghahroodi, Mark Zwolinski, Emre Özer:
Radiation hardening by design: A novel gate level approach. AHS 2011: 74-79 - [c39]Michael Merrett, Plamen Asenov, Yangang Wang, Mark Zwolinski, Dave Reid, Campbell Millar, Scott Roy, Zhenyu Liu, Stephen B. Furber, Asen Asenov:
Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis. DATE 2011: 1537-1540 - [c38]P. Lalith Suresh, Navaneeth Rameshan, Manoj Singh Gaur, Mark Zwolinski, Vijay Laxmi:
Acceleration of Functional Validation Using GPGPU. DELTA 2011: 211-216 - [c37]Massoud Mokhtarpour Ghahroodi, Mark Zwolinski, Rick Wong, Shi-Jie Wen:
Timing Vulnerability Factors of Ultra Deep-sub-micron CMOS. ETS 2011: 202 - [c36]Harsh Gidra, Israrul Haque, Nitin P. Kumar, M. Sargurunathan, Manoj Singh Gaur, Vijay Laxmi, Mark Zwolinski, Virendra Singh:
Parallelizing TUNAMI-N1 Using GPGPU. HPCC 2011: 845-850 - [c35]Manoj Singh Gaur, Vijay Laxmi, Lakshminarayanan V., Kamal Cahndra, Mark Zwolinski:
Acceleration of packet filtering using gpgpu. SIN 2011: 227-230 - 2010
- [j17]Ahmed K. Al-Sulaifanie, Arash Ahmadi, Mark Zwolinski:
Very large scale integration architecture for integer wavelet transform. IET Comput. Digit. Tech. 4(6): 471-483 (2010) - [c34]Andrew D. Brown, Steve B. Furber, Jeff S. Reeve, Peter R. Wilson, Mark Zwolinski, John E. Chad, Luis A. Plana, David R. Lester:
A communication infrastructure for a million processor machine. Conf. Computing Frontiers 2010: 75-76 - [c33]Aisha Fouad Bushager, Mark Zwolinski:
Modelling Smart Card Security Protocols in SystemC TLM. EUC 2010: 637-643 - [c32]Tarek Nechma, Mark Zwolinski, Jeff S. Reeve:
Parallel sparse matrix solver for direct circuit simulations on FPGAs. ISCAS 2010: 2358-2361 - [c31]Michael Merrett, Yangang Wang, Mark Zwolinski, Koushik Maharatna, Massimo Alioto:
Design metrics for RTL level estimation of delay variability due to intradie (random) variations. ISCAS 2010: 2498-2501
2000 – 2009
- 2009
- [j16]Miljana Sokolovic, Vanco B. Litovski, Mark Zwolinski:
New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits. Microelectron. Reliab. 49(2): 186-198 (2009) - [c30]Biswajit Mishra, Bashir M. Al-Hashimi, Mark Zwolinski:
Variation resilient adaptive controller for subthreshold circuits. DATE 2009: 142-147 - [c29]Yangang Wang, Mark Zwolinski:
Analytical Transient Response and Propagation Delay Model for Nanoscale CMOS Inverter. ISCAS 2009: 2998-3001 - 2008
- [j15]Karthik Baddam, Mark Zwolinski:
Path switching: a technique to tolerate dual rail routing imbalances. Des. Autom. Embed. Syst. 12(3): 207-220 (2008) - [c28]Yangang Wang, Mark Zwolinski, Michael Merrett:
Behavioural Modelling for Stability of CMOS SRAM Cells Subject to Random Discrete Doping. BMAS 2008: 136-141 - [c27]Karthik Baddam, Mark Zwolinski:
Divided Backend Duplication Methodology for Balanced Dual Rail Routing. CHES 2008: 396-410 - [c26]Arash Ahmadi, Mark Zwolinski:
Symbolic noise analysis approach to computational hardware optimization. DAC 2008: 391-396 - [c25]Arash Ahmadi, Mark Zwolinski:
On the probability distribution of fixed-point multiplication. ICECS 2008: 25-28 - 2007
- [j14]Reza Asgary, Karim Mohammadi, Mark Zwolinski:
Using neural networks as a fault detection mechanism in MEMS devices. Microelectron. Reliab. 47(1): 142-149 (2007) - [c24]Xiaoxuan She, Mark Zwolinski:
A novel self-routing reconfigurable fault-tolerant cell array. AHS 2007: 725-731 - [c23]Driss Bouami, El Mostapha Aboulhamid, Mohsine Eleuldj, Mark Zwolinski:
General and Technical Program Chairs' Message. ICECS 2007: 1 - [c22]Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi:
Testing of Level Shifters in Multiple Voltage Designs. ICECS 2007: 435-438 - [c21]Arash Ahmadi, Mark Zwolinski:
Multiple-Width Bus Partitioning Approach to Datapath Synthesis. ISCAS 2007: 2994-2997 - [c20]Karthik Baddam, Mark Zwolinski:
Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure. VLSI Design 2007: 854-862 - 2006
- [j13]Vanco B. Litovski, Miona Andrejevic, Mark Zwolinski:
Analogue electronic circuit diagnosis based on ANNs. Microelectron. Reliab. 46(8): 1382-1391 (2006) - [j12]Petros Oikonomakos, Mark Zwolinski:
On the Design of Self-Checking Controllers with Datapath Interactions. IEEE Trans. Computers 55(11): 1423-1434 (2006) - [j11]Petros Oikonomakos, Mark Zwolinski:
An Integrated High-Level On-Line Test Synthesis Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2479-2491 (2006) - [c19]Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod:
Dynamic Voltage Scaling Aware Delay Fault Testing. ETS 2006: 15-20 - [i1]Himanshu Thapliyal, Mark Zwolinski:
Reversible Logic to Cryptographic Hardware: A New Paradigm. CoRR abs/cs/0610089 (2006) - 2005
- [c18]Vanco B. Litovski, Mark Zwolinski, Miona Andrejevic:
Behavioural modelling, simulation, test and diagnosis of MEMS using ANNs. ISCAS (5) 2005: 5182-5185 - 2004
- [j10]Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski:
Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations. J. Electron. Test. 20(1): 11-23 (2004) - [j9]Vanco B. Litovski, Ivan Litovski, Mark Zwolinski:
Concurrent analogue fault simulation, the equation formulation aspect. Int. J. Circuit Theory Appl. 32(6): 487-507 (2004) - [c17]Mark Zwolinski, Andrew D. Brown:
Behavioural modelling of analogue faults in VHDL-AMS - a case study. ISCAS (5) 2004: 632-635 - [c16]Manoj Singh Gaur, Mark Zwolinski:
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique. VLSI Design 2004: 901-906 - 2003
- [j8]Mark Zwolinski, Manoj Singh Gaur:
Integrating testability with design space exploration. Microelectron. Reliab. 43(5): 685-693 (2003) - [j7]Duncan Crutchley, Mark Zwolinski:
Globally convergent algorithms for DC operating point analysis of nonlinear circuits. IEEE Trans. Evol. Comput. 7(1): 2-10 (2003) - [c15]Petros Oikonomakos, Mark Zwolinski, Bashir M. Al-Hashimi:
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric. DATE 2003: 10596-10601 - [c14]Petros Oikonomakos, Mark Zwolinski:
Foundation of Combined Datapath and Controller Self-checking Design. IOLTS 2003: 30-34 - [c13]Andrew D. Brown, Mark Zwolinski:
The continuous-discrete interface - What does this really mean? Modelling and simulation issues. ISCAS (3) 2003: 894-897 - 2002
- [c12]Duncan Crutchley, Mark Zwolinski:
Using evolutionary and hybrid algorithms for DC operating point analysis of nonlinear circuits. IEEE Congress on Evolutionary Computation 2002: 753-758 - [c11]Peter R. Wilson, J. Neil Ross, Mark Zwolinski, Andrew D. Brown, Yavuz Kiliç:
Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS. DATE 2002: 1133 - [c10]Petros Oikonomakos, Mark Zwolinski:
Transformation Based Insertion of On-Line Testing Resources in a High-Level Synthesis Environment. IOLTW 2002: 185 - 2001
- [j6]Mark Zwolinski:
A technique for transparent fault injection and simulation in VHDL. Microelectron. Reliab. 41(6): 797-804 (2001) - [j5]Zheng Rong Yang, Mark Zwolinski:
Mutual Information Theory for Adaptive Mixture Models. IEEE Trans. Pattern Anal. Mach. Intell. 23(4): 396-403 (2001) - [c9]Yavuz Kiliç, Mark Zwolinski:
Process variation independent built-in current sensor for analogue built-in self-test. ISCAS (4) 2001: 398-401 - [c8]Mark Zwolinski, R. W. Allen:
Practical algorithms for fully decoupled mixed-mode simulation of electronic circuits. ISCAS (5) 2001: 451-454 - 2000
- [j4]Zheng Rong Yang, Mark Zwolinski, Chris D. Chalk, Alan Christopher Williams:
Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1): 142-151 (2000) - [c7]Zheng Rong Yang, Mark Zwolinski:
Applying Mutual Information to Adaptive Mixture Models. IDEAL 2000: 250-255
1990 – 1999
- 1999
- [c6]Yavuz Kiliç, Mark Zwolinski:
Testing analog circuits by supply voltage variation and supply current monitoring. CICC 1999: 155-158 - [c5]Zheng Rong Yang, Mark Zwolinski:
Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog Circuits. DATE 1999: 244-248 - 1998
- [c4]Chris D. Chalk, Mark Zwolinski:
A design for test technique to increase the resolution of analogue supply current tests. ICECS 1998: 221-224 - 1997
- [c3]Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski:
Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations. DFT 1997: 100-109 - 1996
- [c2]Mark Zwolinski, Chris D. Chalk, Brian R. Wilkins:
Analogue Fault Modelling and Simulation for Supply Current Monitoring. ED&TC 1996: 547-552 - 1992
- [j3]Andrew D. Brown, Mark Zwolinski, Ken G. Nichols, Tom J. Kazmierski:
Confidence in mixed-mode circuit simulation. Comput. Aided Des. 24(2): 115-118 (1992) - [j2]Keith Richard Baker, Mark Zwolinski:
Interleaving: an additional topological compaction technique for Weinberger array generation. Comput. Aided Des. 24(3): 169-176 (1992) - 1991
- [c1]Tom J. Kazmierski, Andrew D. Brown, Ken G. Nichols, Mark Zwolinski:
A General Purpose Network Solving System. VLSI 1991: 147-156 - 1990
- [j1]Andrew D. Brown, Mark Zwolinski:
Lee router modified for global routing. Comput. Aided Des. 22(5): 296-300 (1990)
Coauthor Index
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load references from crossref.org and opencitations.net
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Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
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OpenAlex data
Load additional information about publications from 
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last updated on 2024-10-02 20:40 CEST by the dblp team
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