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2020 – today
- 2024
[j21]Sin-Han Huang, Tzu-Yin Chao, Beatrice Adelaide Wibisono
, Mark Po-Hung Lin, Ching-Chun Huang:
SSIOE: Self-Supervised Indoor Occupancy Estimation for Intelligent Building Management. IEEE Trans Autom. Sci. Eng. 21(3): 3025-3038 (2024)- [c42]Chia-Wei Lin, Jing-Yao Weng, I-Te Lin, Ho-Chieh Hsu, Chia-Ming Liu, Mark Po-Hung Lin:
Voronoi Diagram-based Multiple Power Plane Generation on Redistribution Layers in 3D ICs. DAC 2024: 19:1-19:6 - [c41]Mark Po-Hung Lin, Chou-Chen Lee, Yi-Chao Hsieh:
Reinforcement Learning or Simulated Annealing for Analog Placement? A Study based on Bounded-Sliceline Grids. ISPD 2024: 143-150 - 2023
- [j20]Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin, Guan-Qi Fang, Simon Yi-Hung Chen:
Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 266-279 (2023) - [j19]A. K. Thasreefa, Abhishek Patyal, Hao-Yu Chi, Mark Po-Hung Lin, Hung-Ming Chen:
On Reducing LDE Variations in Modern Analog Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1268-1279 (2023) - [c40]Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen:
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. ASP-DAC 2023: 352-357 - [c39]Ding-Hao Wang, Shuo-Hung Hsu, Shu-Hsiang Yang, Pei-Ju Lin, Hui-Ting Yang, Mark Po-Hung Lin:
Late Breaking Results: PVT-Sensitive Delay Fitting for High-Performance Computing. DAC 2023: 1-2 - [c38]Po-Chun Wang, Mark Po-Hung Lin, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Layout Synthesis of Analog Primitive Cells with Variational Autoencoder. SMACD 2023: 1-4 - 2022
- [c37]Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar:
Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. ASP-DAC 2022: 114-121 - [c36]Hung-Yun Hsu, Mark Po-Hung Lin:
Automatic Analog Schematic Diagram Generation based on Building Block Classification and Reinforcement Learning. MLCAD 2022: 43-48 - [c35]Cheng-Yu Chiang, Chia-Lin Hu, Kang-Yu Chang, Mark Po-Hung Lin, Shyh-Jye Jou, Hung-Yu Chen, Chien-Nan Jimmy Liu, Hung-Ming Chen:
On Optimizing Capacitor Array Design for Advanced Node SAR ADC. SMACD 2022: 1-4 - [d1]Sin-Han Huang, Tzu-Yin Chao, Mark Po-Hung Lin, Ching-Chun Huang:
Dataset of SSIOE (Self-Supervised Indoor Occupancy Estimation for Intelligent Building Management). IEEE DataPort, 2022
- 2021
- [c34]Meng-Che Wu, Ai Quoc Dao, Mark Po-Hung Lin:
A Novel Technology Mapper for Complex Universal Gates. ASP-DAC 2021: 475-480 - [c33]Ding-Hao Wang, Pei-Ju Lin, Hui-Ting Yang, Ching-An Hsu, Sin-Han Huang, Mark Po-Hung Lin:
A Novel Machine-Learning based SoC Performance Monitoring Methodology under Wide-Range PVT Variations with Unknown Critical Paths. DAC 2021: 1370-1371 - [c32]Kuan-Chun Chen, Chou-Chen Lee, Mark Po-Hung Lin, Yan-Jhih Wang, Yi-Ting Chen:
Massive Figure Extraction and Classification in Electronic Component Datasheets for Accelerating PCB Design Preparation. MLCAD 2021: 1-6 - 2020
- [j18]Yen-Yu Su, Shuo-Hui Wang, Wei-Liang Wu, Mark Po-Hung Lin:
Corner-Stitching-Based Multilayer Obstacle-Avoiding Component-to-Component Rectilinear Minimum Spanning Tree Construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 675-685 (2020) - [c31]Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin:
Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization. DAC 2020: 1-2 - [c30]Tzu-Wei Wang, Po-Chang Wu, Mark Po-Hung Lin:
Late Breaking Results: Automatic Adaptive MOM Capacitor Cell Generation for Analog and Mixed-Signal Layout Design. DAC 2020: 1-2 - [c29]Mark Po-Hung Lin, Hao-Yu Chi, Abhishek Patyal, Zheng-Yao Liu, Jun-Jie Zhao, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Achieving Analog Layout Integrity through Learning and Migration Invited Talk. ICCAD 2020: 55:1-55:8 - [c28]Ing-Chao Lin, Ulf Schlichtmann, Tsung-Wei Huang, Mark Po-Hung Lin:
Overview of 2020 CAD Contest at ICCAD. ICCAD 2020: 67:1-67:3
2010 – 2019
- 2019
- [c27]Shuo-Hui Wang, Guan-Hong Liou, Yen-Yu Su, Mark Po-Hung Lin:
IR-aware Power Net Routing for Multi-Voltage Mixed-Signal Design. DATE 2019: 72-77 - [c26]Ulf Schlichtmann, Sabya Das, Ing-Chao Lin, Mark Po-Hung Lin:
Overview of 2019 CAD Contest at ICCAD. ICCAD 2019: 1-2 - 2018
- [j17]Ai Quoc Dao, Mark Po-Hung Lin, Alan Mishchenko:
SAT-Based Fault Equivalence Checking in Functional Safety Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3198-3205 (2018) - [c25]Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton:
Efficient computation of ECO patch functions. DAC 2018: 51:1-51:6 - [c24]Guan-Hong Liou, Shuo-Hui Wang, Yan-Yu Su, Mark Po-Hung Lin:
Classifying Analog and Digital Circuits with Machine Learning Techniques Toward Mixed-Signal Design Automation. SMACD 2018: 173-176 - 2017
- [j16]Chih-Cheng Hsu, Masanori Hashimoto, Mark Po-Hung Lin:
Minimizing detection-to-boosting latency toward low-power error-resilient circuits. Integr. 58: 236-244 (2017) - [j15]Mark Po-Hung Lin, Vincent Wei-Hao Hsiao, Chun-Yu Lin, Nai-Chen Chen:
Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1274-1286 (2017) - [j14]Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1313-1326 (2017) - [j13]Pang-Yen Chou, Nai-Chen Chen, Mark Po-Hung Lin, Helmut Graeb:
Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2234-2247 (2017) - [c23]Nai-Chen Chen, Pang-Yen Chou, Helmut E. Graeb, Mark Po-Hung Lin:
High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC. DATE 2017: 1757-1762 - [c22]Guo-Gin Fan, Mark Po-Hung Lin:
State retention for power gated design with non-uniform multi-bit retention latches. ICCAD 2017: 607-614 - [c21]Hong Liu, Zheyu Liu, Fei Qiao, Mark Po-Hung Lin, Qi Wei, Huazhong Yang:
AIsim: Functional Simulator for Analog-to-Information Perceptual Systems. ISVLSI 2017: 507-512 - [i1]Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing. CoRR abs/1705.04991 (2017) - 2016
- [j12]Mark Po-Hung Lin, Po-Hsun Chang, Shuenn-Yuh Lee, Helmut E. Graeb:
DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(8): 1229-1242 (2016) - [j11]Po-Hsun Wu, Mark Po-Hung Lin, Xin Li, Tsung-Yi Ho:
Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching. ACM Trans. Design Autom. Electr. Syst. 21(3): 39:1-39:22 (2016) - [c20]Mark Po-Hung Lin, Yao-Wen Chang, Chih-Ming Hung:
Recent research development and new challenges in analog layout synthesis. ASP-DAC 2016: 617-622 - [c19]Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing. DAC 2016: 101:1-101:6 - [c18]Chih-Cheng Hsu, Mark Po-Hung Lin, Masanori Hashimoto:
Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits. SLIP 2016: 2:1-2:6 - 2015
- [j10]Chih-Cheng Hsu, Mark Po-Hung Lin, Yao-Tsung Chang:
Crosstalk-aware multi-bit flip-flop generation for power optimization. Integr. 48: 146-157 (2015) - [j9]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Xin Li, Tsung-Yi Ho:
A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(2): 199-212 (2015) - [j8]Mark Po-Hung Lin, Chih-Cheng Hsu, Yu-Chuan Chen:
Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(2): 280-292 (2015) - [c17]Po-Hsun Wu, Mark Po-Hung Lin, Tsung-Yi Ho:
Analog layout synthesis with knowledge mining. ECCTD 2015: 1-4 - [c16]Po-Hsun Wu, Mark Po-Hung Lin, Xin Li, Tsung-Yi Ho:
Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment. ISPD 2015: 25-31 - [c15]Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin:
Low-power gated clock tree optimization for three-dimensional integrated circuits. VLSI-DAT 2015: 1-4 - 2014
- [j7]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Tsung-Yi Ho, Bin-Da Liu:
Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 879-892 (2014) - [c14]Mark Po-Hung Lin, Vincent Wei-Hao Hsiao, Chun-Yu Lin:
Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC. DAC 2014: 165:1-165:6 - [c13]Shu-Hung Lin, Mark Po-Hung Lin:
More effective power-gated circuit optimization with multi-bit retention registers. ICCAD 2014: 213-217 - [c12]Shih-Chuan Lo, Chih-Cheng Hsu, Mark Po-Hung Lin:
Power optimization for clock network with clock gate cloning and flip-flop merging. ISPD 2014: 77-84 - 2013
- [j6]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen, Shun-Ren Siao, Shu-Hung Lin:
1-D Cell Generation With Printability Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 419-432 (2013) - [j5]Mark Po-Hung Lin, Yi-Ting He, Vincent Wei-Hao Hsiao, Rong-Guey Chang, Shuenn-Yuh Lee:
Common-Centroid Capacitor Layout Generation Considering Device Matching and Parasitic Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(7): 991-1002 (2013) - [c11]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen:
Lithography-aware 1-dimensional cell generation. ECCTD 2013: 1-4 - [c10]Chih-Cheng Hsu, Yu-Chuan Chen, Mark Po-Hung Lin:
In-placement clock-tree aware multi-bit flip-flop generation for power optimization. ICCAD 2013: 592-598 - 2012
- [c9]Chih-Cheng Hsu, Yao-Tsung Chang, Mark Po-Hung Lin:
Crosstalk-aware power optimization with multi-bit flip-flops. ASP-DAC 2012: 431-436 - [c8]Po-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu:
Performance-driven analog placement considering monotonic current paths. ICCAD 2012: 613-619 - 2011
- [j4]Shuenn-Yuh Lee, Chih-Yuan Chen, Jia-Hua Hong, Rong-Guey Chang, Mark Po-Hung Lin:
Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist. Microelectron. J. 42(2): 347-357 (2011) - [j3]Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang:
Thermal-Driven Analog Placement Considering Device Matching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 325-336 (2011) - [j2]Mark Po-Hung Lin, Chih-Cheng Hsu, Yao-Tsung Chang:
Post-Placement Power Optimization With Multi-Bit Flip-Flops. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(12): 1870-1882 (2011) - [c7]Mark Po-Hung Lin:
Recent research in analog placement considering thermal gradient. ECCTD 2011: 349-352 - [c6]Hui-Fang Tsao, Pang-Yen Chou, Shih-Lun Huang, Yao-Wen Chang, Mark Po-Hung Lin, Duan-Ping Chen, Dick Liu:
A corner stitching compliant B∗-tree representation and its applications to analog placement. ICCAD 2011: 507-511 - 2010
- [c5]Yao-Tsung Chang, Chih-Cheng Hsu, Mark Po-Hung Lin, Yu-Wen Tsai, Sheng-Fong Chen:
Post-placement power optimization with multi-bit flip-flops. ICCAD 2010: 218-223
2000 – 2009
- 2009
- [j1]Mark Po-Hung Lin, Yao-Wen Chang, Shyh-Chang Lin:
Analog Placement Based on Symmetry-Island Formulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(6): 791-804 (2009) - [c4]Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang:
Thermal-driven analog placement considering device matching. DAC 2009: 593-598 - [c3]Helmut Gräb, Florin Balasa, Rafael Castro-López, Yu-Wei Chang, Francisco V. Fernández, Mark Po-Hung Lin, Martin Strasser:
Analog layout synthesis - Recent advances in topological approaches. DATE 2009: 274-279 - 2008
- [c2]Mark Po-Hung Lin, Shyh-Chang Lin:
Analog placement based on hierarchical module clustering. DAC 2008: 50-55 - 2007
- [c1]Mark Po-Hung Lin, Shyh-Chang Lin:
Analog Placement Based on Novel Symmetry-Island Formulation. DAC 2007: 465-470
Coauthor Index
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