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ORCIDUtz G. Baitinger
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1990 – 1999
- 1999
[c12]Markus Bühler, Matthias Papesch, K. Kapp, Utz G. Baitinger:
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach. DATE 1999: 459-- [c11]Bernd Stöhr, Utz G. Baitinger:
Eine neue Methode zur Spezifikation von komplexen Steuerwerken unter der Randbedingung der Synthese und eines kurzen Entwurfszyklus. MBMV 1999: 21-30 - 1998
- [c10]K. Kapp, Markus Bühler, D. Dallmann, Utz G. Baitinger:
TESA: Timeparallel Estimation of Switching Activity under a real delay model. ICECS 1998: 233-236 - [c9]Markus Bühler, D. Dallmann, Utz G. Baitinger:
Switching Activity Analysis Using a Set Theoretical Approach. MBMV 1998: 124-130 - 1997
- [c8]Peter E. H. Hofmann, Utz G. Baitinger:
CoDO - Eine Entwurfsumgebung für verteilte objektorientierte CAE-Werkzeuge. Kommunikation in Verteilten Systemen 1997: 211-223 - 1996
- [c7]Michael Ryba, Utz G. Baitinger:
An integrated concept for design project planning and design flow control. EURO-DAC 1996: 98-103 - 1994
- [c6]Utz G. Baitinger:
Hardware Design - A Tools View. IFIP Congress (3) 1994: 326-332 - 1993
- [c5]Michael Ryba, Wolfram Seibold, Utz G. Baitinger, Ulrich Thelen:
Parameterized VHDL Entities for the Simulation of Hybrid Circuits. CHDL 1993: 551-567 - 1992
- [c4]Philipp Lanchès, Utz G. Baitinger:
Eine Umgebung zur Evaluierug paralleler Logiksimulationsverfahren. Transputer-Anwender-Treffen 1992: 61-71 - [c3]Philipp Lanchès, Utz G. Baitinger:
Parallele Vorverarbeitungsschritte für die verteilte Logiksimulation. Transputer-Anwender-Treffen 1992: 214-224 - 1990
- [c2]Frank H. Huentemann, Utz G. Baitinger:
A gate-matrix oriented partitioning approach for multilevel logical networks. EURO-DAC 1990: 327-331
1980 – 1989
- 1989
- [j4]Rainer Amann, Utz G. Baitinger:
Optimal state chains and state codes in finite state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(2): 153-170 (1989) - 1988
- [j3]Helmut Mahler, H. Lieb, Utz G. Baitinger:
Processor control part synthesis using effective partitioning algorithms. Microprocess. Microprogramming 23(1-5): 33-36 (1988) - [j2]Hans-Jörg Mathony, Utz G. Baitinger:
CARLOS: an automated multilevel logic design system for CMOS semi-custom integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(3): 346-355 (1988) - [c1]Rainer Amann, Bernhard Eschermann, Utz G. Baitinger:
PLA based finite state machines using Johnson counters as state memories. ICCD 1988: 267-270 - 1984
- [j1]Utz G. Baitinger, Roland Schmid:
Der rechnergestützte "Floor-Plan" und seine Rolle beim Entwurf höchstintegrierter Schaltungen / The role of floor-plan tools in the VLSI design process. Elektron. Rechenanlagen 26(6): 290-297 (1984)
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