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Jyi-Tsong Lin
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2020 – today
- 2023
- [c9]Yen-Chen Chang, Wei-Heng Tai, Jyi-Tsong Lin:
Steeper Subthreshold Swing Attained in Ge-Source Inductive Tunneling FET via Epitaxial Tunnel Layer for Suppressed Point Tunneling. ASICON 2023: 1-4 - [c8]Jyi-Tsong Lin, Kuan-Pin Lin:
A Simple New Line-Tunneling iTFET with Overlapping Between Gate and Source Contact. ASICON 2023: 1-4 - [c7]Ho-Hin Tse, Zheng-Hong Zhong, Jyi-Tsong Lin:
An iTFET with Control Gate for Low Power Applications in RF and Digital Circuits. ASICON 2023: 1-4 - 2020
- [c6]Yu-Jen Chen, Jyi-Tsong Lin:
Performances Improvement of Tunneling Field-Effect Transistors' with the Advanced Double-Gate PN Construction. ICCE-TW 2020: 1-2 - no results
2010 – 2019
- 2018
- [c5]Md. Hasan Raza Ansari, Nupur Navlakha
, Jyi-Tsong Lin, Abhinav Kranti:
Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory. VLSID 2018: 422-427 - 2017
- [j2]Chun-Yu Chen, Jyi-Tsong Lin, Meng-Hsueh Chiang
:
Threshold-voltage variability analysis and modeling for junctionless double-gate transistors. Microelectron. Reliab. 74: 22-26 (2017) - 2015
- [c4]Wei-Han Lee, Jyi-Tsong Lin, Yu-Chun Wang, Po-Hsieh Lin, Chien-Chia Lai, Yong-Huang Lin, Tin-Chun Chang:
Using GIDL mechanism for low-power consumption and data retention time improvement in a double-gate nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body structure. ASICON 2015: 1-4 - 2011
- [c3]Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Tung-Yen Lai, Fu-Liang Yang:
A unipolar-CMOS with recessed source/drain load. ASICON 2011: 543-546 - no results
2000 – 2009
- 2008
- [j1]Jyi-Tsong Lin, Yi-Chuen Eng:
Analysis of Block Oxide Height Variations for a 40nm Gate Length bFDSOI-FET. J. Comput. 3(5): 41-45 (2008) - 2007
- [c2]Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin:
Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI. VLSI Design 2007: 653-656 - 2006
- [c1]Jyi-Tsong Lin, Mike Chang:
A New 1T DRAM Cell With Enhanced Floating Body Ef. MTDT 2006: 23-27 - no results
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