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2020 – today
- 2025
[j65]Qiang Zhang
, Mingyue Cui, Weichong Chen, Yue Liu, Zhiyi Yu:
UIC: A unified and scalable chip integrating neuromorphic computation and general purpose processor. Microelectron. J. 155: 106449 (2025)- [j64]Jinghai Wang, Shanlin Xiao, Jilong Luo, Bo Li, Lingfeng Zhou, Zhiyi Yu:
An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS. IEEE Trans. Very Large Scale Integr. Syst. 33(1): 154-167 (2025) - 2024
- [j63]Zhiyi Yu, Hong Li, Jialin Feng:
Enhancing text classification with attention matrices based on BERT. Expert Syst. J. Knowl. Eng. 41(3) (2024) - [j62]Jialin Feng, Hong Li, Zhiyi Yu:
Enhancing aspect-based sentiment analysis with dependency-attention GCN and mutual assistance mechanism. J. Intell. Inf. Syst. 62(1): 163-189 (2024) - [j61]Wei Liu, Shanlin Xiao, Yue Liu, Zhiyi Yu:
SC-PLR: An Approximate Spiking Neural Network Accelerator With On-Chip Predictive Learning Rule. IEEE Trans. Biomed. Circuits Syst. 18(5): 1156-1165 (2024) - [j60]Wanyuan Pan, Yihe Yu, Chengcheng Tang, Ningyuan Yin, Zhiyi Yu:
Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3538-3542 (2024) - [j59]Huiyao Wang, Shanlin Xiao, Lingfeng Zhou, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu:
LAC: A Novel Lightweight Asynchronous Controller With Optimized Phase Shift. IEEE Trans. Circuits Syst. II Express Briefs 71(8): 3920-3924 (2024) - [j58]Zhiyi Yu, Hong Li, Jialin Feng:
Contrastive learning for unsupervised sentence embeddings using negative samples with diminished semantics. J. Supercomput. 80(4): 5428-5445 (2024) - [j57]Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu:
Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1045-1057 (2024) - [j56]Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu:
Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1852-1863 (2024) - [c68]Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu:
An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint. DATE 2024: 1-6 - [c67]Yue Liu, Shanlin Xiao, Bo Li, Zhiyi Yu:
Sparsespikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer. ICASSP 2024: 6410-6414 - [c66]Baiqing Zhong, Mingyu Wang, Yicong Zhang, Xiaojie Li, Zhiyi Yu:
CCacheSim: A Circuit-Architecture Cross-Level Simulation Framework for SRAM-Based in-Cache Computing System Evaluation. ICCD 2024: 583-590 - [c65]Xiaojie Li, Mingyu Wang, Yangzhan Mai, Yicong Zhang, Baiqing Zhong, Zhiyi Yu:
BafSP: Co-Design of Compute SRAM and Bit-Aware Data Flip Mitigation with In-Memory Sparsity Detection for SpMM. ISVLSI 2024: 124-129 - [c64]Yukun Wei, Mingyu Wang, Haiqiu Huang, Wangguang Wang, Zhiyi Yu:
DAW-DMR: Divergence-Aware Warped DMR with Full Error Detection for GPGPU s. ISVLSI 2024: 161-166 - [c63]Yicong Zhang, Mingyu Wang, Wangguang Wang, Yangzhan Mai, Haiqiu Huang, Zhiyi Yu:
Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations. MICRO 2024: 671-685 - [c62]Ruibin Zhou, Yuhan Wang, Jian Huang, Xinrui Zhang, Xianping Liu, Zhiyi Yu:
An Adaptive Re-Read Strategy for Mitigating Temporary Read Errors in 3D-NAND Flash Solid-State Drives. NVMSA 2024: 1-2 - 2023
- [j55]Xing Jin, Ningyuan Yin, Weichong Chen, Ximing Li, Guihua Zhao, Zhiyi Yu:
A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations. IEICE Electron. Express 20(11): 20230152 (2023) - [j54]Xiangyu Meng, Kangfeng Wei, Zhiyi Yu, Xinlun Cai:
A Low Power 100-Gb/s PAM-4 Driver with Linear Distortion Compensation in 65-nm CMOS. IEICE Trans. Electron. 106(1): 7-13 (2023) - [j53]Xiangyu Meng, Yecong Li, Zhiyi Yu:
A Low Insertion Loss Wideband Bonding-Wire Based Interconnection for 400 Gbps PAM4 Transceivers. IEICE Trans. Electron. 106(1): 14-19 (2023) - [j52]Guihua Zhao, Yating Peng, Yizhan Wang, Caihua Wan, Xianping Liu, Yu Zhang, Xiufeng Han, Weichong Chen, Zhiyi Yu:
Computing Resistance-Style Image Sensors for Artificial Neural Networks. IEEE Internet Things J. 10(6, March 15): 4985-4997 (2023) - [j51]Yicong Zhang, Mingyu Wang, Wangguang Wang, Zhiyi Yu:
Re-Cache: Mitigating cache contention by exploiting locality characteristics with reconfigurable memory hierarchy for GPGPUs. Microelectron. J. 138: 105825 (2023) - [j50]Ximing Li, Xing Jin, Weichong Chen, Ningyuan Yin, Zhiyi Yu:
Parallel-Prefix Adder in Spin-Orbit Torque Magnetic RAM for High Bit-Width Non-Volatile Computation. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 761-765 (2023) - [j49]Xing Jin, Weichong Chen, Ximing Li, Ningyuan Yin, Caihua Wan, Mingkun Zhao, Xiufeng Han, Zhiyi Yu:
High-Reliability, Reconfigurable, and Fully Non-volatile Full-Adder Based on SOT-MTJ for Image Processing Applications. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 781-785 (2023) - [j48]Chuanghao Zhang, Mingyu Wang, Yangzhan Mai, Chengcheng Tang, Zhiyi Yu:
A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3589-3593 (2023) - [j47]Yicong Zhang, Mingyu Wang, Yangzhan Mai, Zhiyi Yu:
TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2030-2043 (2023) - [c61]Jiahua Yan, Mingyu Wang, Yao Qin, Zhiyi Yu:
CRAFT: Common Router Architecture for Throughput Optimization. ICA3PP (3) 2023: 212-229 - [c60]Wangguang Wang, Mingyu Wang, Yicong Zhang, Yukun Wei, Zhiyi Yu:
LWSDP: Locality-Aware Warp Scheduling and Dynamic Data Prefetching Co-design in the Per-SM Private Cache of GPGPUs. ICPADS 2023: 1230-1237 - [c59]Xiaoran Zhang, Mingyu Wang, Yicong Zhang, Tao Lu, Zhiyi Yu:
A Scalable Deadlock-Free Static Routing Algorithm for Chiplet-Based Systems. ICPADS 2023: 1350-1357 - [c58]Zeyang Xu, Shanlin Xiao, Lingfeng Zhou, Bohan Wang, Zhiyi Yu:
Towards Energy-Efficient Asynchronous Circuit Design with Flip-Flop-to-Latch Replacement. ICTA 2023: 35-36 - [c57]Kexin Huang, Wei Liu, Yue Liu, Shanlin Xiao, Zhiyi Yu:
Towards Efficient On-Chip Learning for Spiking Neural Networks Accelerator with Surrogate Gradient. ICTA 2023: 89-90 - [c56]Yangzhan Mai, Mingyu Wang, Chuanghao Zhang, Baiqing Zhong, Zhiyi Yu:
A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips. ISCAS 2023: 1-5 - [c55]Baiqing Zhong, Mingyu Wang, Chuanghao Zhang, Yangzhan Mai, Xiaojie Li, Zhiyi Yu:
A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference. ISVLSI 2023: 1-6 - [i5]Jilong Luo, Shanlin Xiao, Yinsheng Chen, Zhiyi Yu:
Enabling energy-Efficient object detection with surrogate gradient descent in spiking neural networks. CoRR abs/2310.12985 (2023) - [i4]Yue Liu, Shanlin Xiao, Bo Li, Zhiyi Yu:
SparseSpikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer. CoRR abs/2311.08806 (2023) - 2022
- [j46]Guihua Zhao, Xing Jin, Huafeng Ye, Yating Peng, Wei Liu, Ningyuan Yin, Weichong Chen, Jianjun Chen, Ximing Li, Zhiyi Yu:
An in-memory computing multiply-and-accumulate circuit based on ternary STT-MRAMs for convolutional neural networks. IEICE Electron. Express 19(20): 20220399 (2022) - [j45]Wenzha Yang, Yong Ma, Jiajie Yan, Yang Chen, Shanlin Xiao, Zhiyi Yu:
A dual-rail/single-rail hybrid system using null convention logic circuits. Microelectron. J. 125: 105446 (2022) - [j44]Yuhao Huang, Shanlin Xiao, Zhiyu Li, Zhiyi Yu:
An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3904-3908 (2022) - [c54]Zhiyi Yu, Chao Li, Chaochen Hu, Zhen Chen, Yandong Yao, Jiang Wu, Hao Wang, Jialun Du, Min Guo, Haoyu Wang, Weimin Li, Xiu Li, Xiaodong Ma, Yisong Zhang, Shuangshou Li:
One Case of THOUGHT: Industry-University Converged Education Practice on Open Source. ICCSE (3) 2022: 289-303 - [c53]Ruimin Zhu, Zeyang Xu, Yuhao Huang, Shanlin Xiao, Zhiyi Yu:
DFT Architecture for Click-Based Bundled-Data Asynchronous Circuits. ICTA 2022: 88-89 - [c52]Sheng Zuo, Junjie Zhuang, Yao Liu, Mingyu Wang, Zhiyi Yu:
Hardware Based RISC-V Instruction Set Randomization. ICTA 2022: 96-97 - [c51]Huafeng Ye, Huipeng Deng, Jian Wang, Mingyu Wang, Zhiyi Yu:
3D-NWA: A Nested-Winograd Accelerator for 3D CNNs. ICTA 2022: 143-144 - 2021
- [j43]Bin Zheng, Zhengbao Lei, Chen Tang, Jin Wang, Zhuofan Liao, Zhiyi Yu, Yiming Xie:
OERFF: A Vehicle Re-Identification Method Based on Orientation Estimation and Regional Feature Fusion. IEEE Access 9: 66661-66674 (2021) - [j42]Huipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng, Zhiyi Yu:
Dimension fusion: Dimension-level dynamically composable accelerator for convolutional neural networks. IEICE Electron. Express 18(24): 20210491 (2021) - [j41]Mingyuan Meng, Xingyu Yang, Lei Bi, Jinman Kim, Shanlin Xiao, Zhiyi Yu:
High-parallelism Inception-like Spiking Neural Networks for Unsupervised Feature Learning. Neurocomputing 441: 92-104 (2021) - [j40]Qiang Zhang, Shanlin Xiao, Zhiyi Yu, Huanliang Zheng, Peng Wang:
Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing. J. Electronic Imaging 30(6) (2021) - [j39]Shanlin Xiao, Weikun Liu, Junshu Lin, Zhiyi Yu:
A Data-Driven Asynchronous Neural Network Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(9): 1874-1886 (2021) - [j38]Ningyuan Yin, Baofa Huang, Xiaobai Chen, Jianjun Chen, Zhiyi Yu:
An MTJ-Based Asynchronous System With Extremely Fine-Grained Voltage Scaling. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 311-321 (2021) - [j37]Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, Zhiyi Yu:
A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3153-3157 (2021) - [j36]Huanliang Zheng, Yuhao Guo, Xingyu Yang, Shanlin Xiao, Zhiyi Yu:
Balancing the Cost and Performance Trade-Offs in SNN Processors. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3172-3176 (2021) - [c50]Huipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng, Zhiyi Yu:
3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA. FCCM 2021: 181-185 - [c49]Jian Wang, Huipeng Deng, Huafeng Ye, Shanlin Xiao, Zhiyi Yu:
FWUA : A Flexible Winograd-Based Uniform Accelerator for 1D/2D/3D CNNs. ICTA 2021: 72-73 - [c48]Qingyi Xie, Ziyuan Luo, Shanlin Xiao, Kai Wang, Zhiyi Yu:
High-Throughput Zipper Encoder for 800G Optical Communication System. ICTA 2021: 214-215 - [c47]Ziyuan Luo, Qingyi Xie, Shanlin Xiao, Zhiyi Yu:
A high throughput spatially coupled low density generator matrix coding system. ICTA 2021: 228-229 - 2020
- [j35]Jianmin Zeng, Zhang Zhang, Runhao Chen, Shiyue Liang, Tianlin Cao, Zhiyi Yu, Xin Cheng, Guangjun Xie:
DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing. IEICE Electron. Express 17(4): 20200005 (2020) - [j34]Shanlin Xiao, Wei Liu, Yuhao Guo, Zhiyi Yu:
Low-Cost Adaptive Exponential Integrate-and-Fire Neuron Using Stochastic Computing. IEEE Trans. Biomed. Circuits Syst. 14(5): 942-950 (2020) - [j33]Shanlin Xiao, Yuhao Guo, Wenkang Liao, Huipeng Deng, Yi Luo, Huanliang Zheng, Jian Wang, Cheng Li, Gezi Li, Zhiyi Yu:
NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 1966-1978 (2020) - [c46]Xingyu Yang, Mingyuan Meng, Shanlin Xiao, Zhiyi Yu:
SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs. ICPR 2020: 6417-6424 - [c45]Junshu Lin, Weikun Liu, Xusheng Li, Shanlin Xiao, Zhiyi Yu:
An Asynchronous Convolution Process Engine forVGG-16 Neural Network. ICTA 2020: 73-74 - [c44]Weikun Liu, Junshu Lin, Xusheng Li, Shanlin Xiao, Zhiyi Yu:
A Low-Power Processing Element Based on Asynchronous Data-Driven Bit-Serial Multiplier for CNNs. ICTA 2020: 79-80 - [c43]Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu:
Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks. IJCNN 2020: 1-8 - [c42]Wenkang Liao, Yuhao Guo, Shanlin Xiao, Zhiyi Yu:
A Low-Cost and High-Throughput NoC-Aware Chip-to-Chip Interconnection. ISCAS 2020: 1-5 - [i3]Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu:
BioSNet: A Fast-Learning and High-Robustness Unsupervised Biomimetic Spiking Neural Network. CoRR abs/2001.01680 (2020) - [i2]Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu:
Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks. CoRR abs/2001.10696 (2020) - [i1]Xingyu Yang, Mingyuan Meng, Shanlin Xiao, Zhiyi Yu:
SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs. CoRR abs/2010.09690 (2020)
2010 – 2019
- 2019
- [j32]Xiaobai Chen, Jinglong Xu, Zhiyi Yu:
A 68-mw 2.2 Tops/w Low Bit Width and Multiplierless DCNN Object Detection Processor for Visually Impaired People. IEEE Trans. Circuits Syst. Video Technol. 29(11): 3444-3453 (2019) - 2018
- [j31]Xiaobai Chen, Zhiyi Yu:
A Flexible and Energy-Efficient Convolutional Neural Network Acceleration With Dedicated ISA and Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1408-1412 (2018) - [c41]Xiaobai Chen, Shanlin Xiao, Zhiyi Yu:
A Reconfigurable Process Engine for Flexible Convolutional Neural Network Acceleration. APSIPA 2018: 1402-1405 - [c40]Ming-e Jing, Yujie Huang, Yibo Fan, Xiaoyong Xue, Xiaoyang Zeng, Zhiyi Yu:
An Automatic Task Partition Method for Multi-core System. ISCAS 2018: 1-5 - 2017
- [j30]Jianmin Zeng, Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie, Jun Han, Xiaoyang Zeng, Zhiyi Yu:
A multi-core-based heterogeneous parallel turbo decoder. IEICE Electron. Express 14(18): 20170768 (2017) - [j29]Sai Manoj P. D., Jie Lin, Shikai Zhu, Yingying Yin, Xu Liu, Xiwei Huang, Chongshen Song, Wenqi Zhang, Mei Yan, Zhiyi Yu, Hao Yu:
A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(6): 1432-1443 (2017) - [j28]Weijing Shi, Xin Li, Zhiyi Yu, Gary Overett:
An FPGA-Based Hardware Accelerator for Traffic Sign Detection. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1362-1372 (2017) - [c39]Xiaobai Chen, Jinlong Xu, Zhiyi Yu:
A fast and energy efficient FPGA-based system for real-time object tracking. APSIPA 2017: 965-968 - [c38]Baofa Huang, Ningyuan Yin, Zhiyi Yu:
The write deduplication mechanism based on a novel low-power data latched sense amplifier for a magnetic tunnel junction based non-volatile memory. ASICON 2017: 383-386 - [c37]Jianwei Yang, Weizhen Wang, Zhicheng Xie, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design. ASICON 2017: 953-956 - 2015
- [j27]Yawei Guo, Yue Wu, Dongdong Guo, Xu Cheng, Zhiyi Yu, Xiaoyang Zeng:
Non-binary digital calibration for split-capacitor DAC in SAR ADC. IEICE Electron. Express 12(4): 20150001 (2015) - [j26]Masoud Daneshtalab, Farhad Mehdipour, Zhiyi Yu, Hannu Tenhunen:
Special Issue on Emerging Many-Core Systems for Exascale Computing. ACM J. Emerg. Technol. Comput. Syst. 11(4): 39:1-39:2 (2015) - [j25]Jun Han, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, Xiaoyang Zeng:
A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1372-1381 (2015) - [j24]Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng:
A 65 nm Cryptographic Processor for High Speed Pairing Computation. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 692-701 (2015) - [j23]Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han, Xingxing Zhang, Zhang Zhang, Xu Cheng, Zhiyi Yu:
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1365-1369 (2015) - [j22]Jianming Yu, Wei Zhou, Yueming Yang, Xiaodong Zhang, Zhiyi Yu:
Many-Core Processors Granularity Evaluation by Considering Performance, Yield, and Lifetime Reliability. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2043-2053 (2015) - [c36]Yi Ren, Jun Han, Zhiyi Yu, Sizhong Xuan, Xiaoyang Zeng:
A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals. ASICON 2015: 1-4 - [c35]Jielin Wang, Weizhen Wang, Jianwei Yang, Zhiyi Yu, Jun Han, Xiaoyang Zeng:
Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design. ASICON 2015: 1-4 - [c34]Sizhong Xuan, Jun Han, Zhiyi Yu, Yi Ren, Xiaoyang Zeng:
A configurable SoC design for information security. ASICON 2015: 1-4 - [c33]Jie Lin, Shikai Zhu, Zhiyi Yu, Dongjun Xu, Sai Manoj P. D., Hao Yu:
A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer. CICC 2015: 1-4 - 2014
- [j21]Yi Li, Liang Wen, Yuejun Zhang, Xu Cheng, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. IEICE Electron. Express 11(3): 20130992 (2014) - [j20]Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng:
A 16-Core Processor With Shared-Memory and Message-Passing Communications. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(4): 1081-1094 (2014) - [j19]Zheng Yu, Zhiyi Yu, Xueqiu Yu, Ningxi Liu, Xiaoyang Zeng:
Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process. IEEE Trans. Circuits Syst. II Express Briefs 61-II(6): 423-427 (2014) - [j18]Renfeng Dou, Jun Han, Yifan Bo, Zhiyi Yu, Xiaoyang Zeng:
An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2245-2255 (2014) - [c32]Lijun Zhou, Zhiyi Yu, Jie Lin, Shikai Zhu, Weijing Shi, Haijie Zhou, Kunpeng Song, Xiaoyang Zeng:
Acceleration of Naive-Bayes algorithm on multicore processor for massive text classification. ISIC 2014: 344-347 - 2013
- [j17]Pengjun Wang, Yuejun Zhang, Jun Han, Zhiyi Yu, Yibo Fan, Zhang Zhang:
Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(5): 963-970 (2013) - [j16]Jun Han, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng:
Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2325-2330 (2013) - [c31]Jie Lin, Wei Zhou, Zhiyi Yu, Xiaoyang Zeng:
A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networks. ASICON 2013: 1-4 - [c30]Zongyan Wang, Dexue Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng:
A fast multi-core virtual platform and its application on software development. ASICON 2013: 1-4 - [c29]Haofan Yang, Kedong Chen, Shengqiong Xie, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng:
Efficient implementation of 3780-point FFT on a 16-core processor. ASICON 2013: 1-4 - [c28]Qing Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng:
A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform. ASICON 2013: 1-4 - [c27]Wei Zhou, Jianming Yu, Jie Lin, Zhiyi Yu, Xiaoyang Zeng:
A 2D mesh NoC with self-configurable and shared-FIFOs routers. ASICON 2013: 1-4 - [c26]Shikai Zhu, Zheng Yu, Shile Cui, Zhiyi Yu, Xiaoyang Zeng:
H.264 video parallel decoder on a 24-core processor. ASICON 2013: 1-4 - [c25]Zheng Yu, Jiajie Zhang, Xueqiu Yu, Xiaoyang Zeng, Zhiyi Yu:
A low power register file with asynchronously controlled read-isolation and software-directed write-discarding. ISCAS 2013: 349-352 - [c24]Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Liyang Zhou:
Time-Division-Multiplexer based routing algorithm for NoC system. ISCAS 2013: 1652-1655 - [c23]Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Jiayi Sheng, Haofan Yang:
Implementation and optimization of 3780-point FFT on multi-core system. ISCAS 2013: 1656-1659 - [c22]Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming-e Jing, Xiaoyang Zeng, Zhiyi Yu:
A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array. ISSCC 2013: 56-57 - [c21]Jiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, Axel Jantsch:
Efficient distributed memory management in a multi-core H.264 decoder on FPGA. ISSoC 2013: 1-4 - 2012
- [j15]Yuejun Zhang, Pengjun Wang, Baoyu Xiong, Zhiyi Yu:
Design of a high information-density multiple valued 2-read 1-write register file. IEICE Electron. Express 9(11): 958-964 (2012) - [j14]Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng:
A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. IEICE Electron. Express 9(16): 1355-1361 (2012) - [j13]Wenhua Fan, Chen Chen, Yun Chen, Zhiyi Yu, Xiaoyang Zeng:
Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform. IEICE Trans. Commun. 95-B(4): 1241-1248 (2012) - [j12]Bei Huang, Kaidi You, Yun Chen, Zhiyi Yu, Xiaoyang Zeng:
A Fully Programmable Reed-Solomon Decoder on a Multi-Core Processor Platform. IEICE Trans. Inf. Syst. 95-D(12): 2939-2947 (2012) - [c20]Liyang Zhou, Ming-e Jing, Liulin Zhong, Zhiyi Yu, Xiaoyang Zeng:
Task-binding based branch-and-bound algorithm for NoC mapping. ISCAS 2012: 648-651 - [c19]Yan Ying, Kaidi You, Liyang Zhou, Heng Quan, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng:
A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost. ISCAS 2012: 2609-2612 - [c18]Yueming Yang, Zewen Shi, Jianming Yu, Liulin Zhong, Xiaoyang Zeng, Zhiyi Yu:
Evaluating performance of manycore processors with various granularities considering yield and lifetime reliability. ISCAS 2012: 2713-2716 - [c17]Yun Chen, Yuebin Huang, Wei Meng, Zhiyi Yu, Xiaoyang Zeng:
A low-cost architecture for multi-mode Reed-Solomon decoder. ISOCC 2012: 332-334 - [c16]Zhiyi Yu, Kaidi You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, Haofan Yang, Ming-e Jing, Xiaoyang Zeng:
An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. ISSCC 2012: 64-66 - 2011
- [j11]Zewen Shi, Xiaoyang Zeng, Zhiyi Yu:
A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs. IEICE Trans. Inf. Syst. 94-D(7): 1386-1397 (2011) - [c15]Jiayi Sheng, Liulin Zhong, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng:
A method of quadratic programming for mapping on NoC architecture. ASICON 2011: 200-203 - [c14]Maofei He, Jiajie Zhang, Wenhua Fan, Zhiyi Yu, Xiaoyang Zeng:
A channel estimator for LTE downlink mapped on a multi-core processor platform. ASICON 2011: 204-207 - [c13]Yueming Yang, Heng Quan, Zewen Shi, Xiaoyang Zeng, Zhiyi Yu:
Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs. ASICON 2011: 267-270 - [c12]Baoyu Xiong, Xingxing Zhang, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
Design of a single-ended cell based 65nm 32×32b 4R2W register file. ASICON 2011: 311-314 - [c11]Liulin Zhong, Jiayi Sheng, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Dian Zhou:
An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture. ASICON 2011: 389-392 - [c10]Jun Han, Xingxing Zhang, Baoyu Xiong, Zhiyi Yu, Xiaoyang Zeng:
A control scheme for a 65nm 32×32b 4-read 2-write register file. ASICON 2011: 739-742 - [c9]Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng:
A low power 1.0 GHz VCO in 65nm-CMOS LP-process. ASICON 2011: 1006-1009 - [c8]Zhiyi Yu, Zewen Shi, Xiaoyang Zeng:
Fault tolerant computing for stream DSP applications using GALS multi-core processors. ISCAS 2011: 2305-2308 - [c7]Zewen Shi, Yueming Yang, Xiaoyang Zeng, Zhiyi Yu:
A reconfigurable and deadlock-free routing algorithm for 2D Mesh Network-on-Chip. ISCAS 2011: 2934-2937 - 2010
- [j10]Yan Ying, Dan Bao, Zhiyi Yu, Xiaoyang Zeng, Yun Chen:
A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(8): 1415-1424 (2010) - [j9]Zhiyi Yu, Bevan M. Baas:
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 750-762 (2010) - [c6]Zewen Shi, Kaidi You, Yan Ying, Bei Huang, Xiaoyang Zeng, Zhiyi Yu:
A scalable and fault-tolerant routing algorithm for NoCs. ISCAS 2010: 165-168
2000 – 2009
- 2009
- [j8]Dean Nguyen Truong, Wayne H. Cheng, Tinoosh Mohsenin, Zhiyi Yu, Anthony T. Jacobson, Gouri Landge, Michael J. Meeuwsen, Christine Watnik, Anh Thien Tran, Zhibin Xiao, Eric W. Work, Jeremy W. Webb, Paul Vincent Mejia, Bevan M. Baas:
A 167-Processor Computational Platform in 65 nm CMOS. IEEE J. Solid State Circuits 44(4): 1130-1144 (2009) - [j7]Zhiyi Yu, Bevan M. Baas:
High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 66-79 (2009) - 2008
- [j6]Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Dean Truong, Tinoosh Mohsenin, Bevan M. Baas:
AsAP: An Asynchronous Array of Simple Processors. IEEE J. Solid State Circuits 43(3): 695-705 (2008) - [j5]Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas:
Architecture and Evaluation of an Asynchronous Array of Simple Processors. J. Signal Process. Syst. 53(3): 243-259 (2008) - [c5]Zhiyi Yu, Bevan M. Baas:
A low-area interconnect architecture for chip multiprocessors. ISCAS 2008: 2857-2860 - 2007
- [j4]Michael J. Meeuwsen, Zhiyi Yu, Bevan M. Baas:
A Shared Memory Module for Asynchronous Arrays of Processors. EURASIP J. Embed. Syst. 2007 (2007) - [j3]Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung:
AsAP: A Fine-Grained Many-Core Platform for DSP Applications. IEEE Micro 27(2): 34-45 (2007) - [j2]Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, Tinoosh Mohsenin, Bevan M. Baas:
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1125-1134 (2007) - 2006
- [c4]Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Daniel Gurman, Chi Chen, Jason Cheung, Dean Truong, Tinoosh Mohsenin:
Hardware and applications of AsAP: An asynchronous array of simple processors. Hot Chips Symposium 2006: 1-31 - [c3]Zhiyi Yu, Bevan M. Baas:
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. ICCD 2006: 174-179 - [c2]Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Mandeep Singh, Bevan M. Baas:
An asynchronous array of simple processors for dsp applications. ISSCC 2006: 1696-1705 - [c1]Zhiyi Yu, Bevan M. Baas:
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems. ISVLSI 2006: 378-383
1990 – 1999
- 1998
- [j1]Matthias Passlack, Ronald N. Legge, Diana Convey, Zhiyi Yu, Jonathan K. Abrokwah:
Optical measurement system for characterizing compound semiconductor interface and surface states. IEEE Trans. Instrum. Meas. 47(5): 1362-1366 (1998)
Coauthor Index
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