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2020 – today
- 2024
[j17]Ben Perach
, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky:
Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. IEEE Trans. Emerg. Top. Comput. 12(1): 7-22 (2024)- [c27]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
PyPIM: Integrating Digital Processing-in-Memory from Microarchitectural Design to Python Tensors. MICRO 2024: 1632-1647 - [i22]Rotem Ben Hur, Orian Leitersdorf, Ronny Ronen, Lidor Goldshmidt, Idan Magram, Lior Kaplun, Leonid Yavitz, Shahar Kvatinsky:
Accelerating DNA Read Mapping with Digital Processing-in-Memory. CoRR abs/2411.03832 (2024) - 2023
- [j16]Orian Leitersdorf, Dean Leitersdorf, Jonathan Gal, Mor M. Dahan, Ronny Ronen, Shahar Kvatinsky:
AritPIM: High-Throughput In-Memory Arithmetic. IEEE Trans. Emerg. Top. Comput. 11(3): 720-735 (2023) - [c26]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
On Consistency for Bulk-Bitwise Processing-in-Memory. HPCA 2023: 705-717 - [c25]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. NEWCAS 2023: 1-5 - [c24]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. SOCC 2023: 1-6 - [i21]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. CoRR abs/2302.01675 (2023) - [i20]Orian Leitersdorf, Yahav Boneh, Gonen Gazit, Ronny Ronen, Shahar Kvatinsky:
FourierPIM: High-Throughput In-Memory Fast Fourier Transform and Polynomial Multiplication. CoRR abs/2304.02336 (2023) - [i19]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
ConvPIM: Evaluating Digital Processing-in-Memory through Convolutional Neural Network Acceleration. CoRR abs/2305.04122 (2023) - [i18]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. CoRR abs/2307.00658 (2023) - [i17]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
CUDA-PIM: End-to-End Integration of Digital Processing-in-Memory from High-Level C++ to Microarchitectural Design. CoRR abs/2308.14007 (2023) - 2022
- [j15]Wei Wang, Barak Hoffer, Tzofnat Greenberg-Toledo, Yang Li, Minhui Zou, Eric Herbelin, Ronny Ronen, Xiaoxin Xu, Yulin Zhao, Jianguo Yang, Shahar Kvatinsky:
Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices. Adv. Intell. Syst. 4(5) (2022) - [j14]Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky:
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. ACM J. Emerg. Technol. Comput. Syst. 18(2): 43:1-43:29 (2022) - [j13]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
MultPIM: Fast Stateful Multiplication for Processing-in-Memory. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1647-1651 (2022) - [c23]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic. ISCAS 2022: 215-219 - [c22]Batel Oved, Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory. MOCAST 2022: 1-4 - [i16]Wei Wang, Barak Hoffer, Tzofnat Greenberg-Toledo, Yang Li, Minhui Zou, Eric Herbelin, Ronny Ronen, Xiaoxin Xu, Yulin Zhao, Jianguo Yang, Shahar Kvatinsky:
Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices. CoRR abs/2203.07884 (2022) - [i15]Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky:
PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. CoRR abs/2203.10486 (2022) - [i14]Batel Oved, Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory. CoRR abs/2205.13559 (2022) - [i13]Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky:
FiltPIM: In-Memory Filter for DNA Sequencing. CoRR abs/2205.15140 (2022) - [i12]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
PartitionPIM: Practical Memristive Partitions for Fast Processing-in-Memory. CoRR abs/2206.04200 (2022) - [i11]Orian Leitersdorf, Dean Leitersdorf, Jonathan Gal, Mor M. Dahan, Ronny Ronen, Shahar Kvatinsky:
AritPIM: High-Throughput In-Memory Arithmetic. CoRR abs/2206.04218 (2022) - [i10]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic. CoRR abs/2206.15165 (2022) - [i9]Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky:
abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory. CoRR abs/2208.14472 (2022) - [i8]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
On Consistency for Bulk-Bitwise Processing-in-Memory. CoRR abs/2211.07542 (2022) - 2021
- [j12]Adi Eliahu, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures. ACM J. Emerg. Technol. Comput. Syst. 17(2): 24:1-24:27 (2021) - [c21]Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. DAC 2021: 199-204 - [c20]Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky:
FiltPIM: In-Memory Filter for DNA Sequencing. ICECS 2021: 1-4 - [c19]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
Making Memristive Processing-in-Memory Reliable. ICECS 2021: 1-6 - [i7]Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. CoRR abs/2105.04212 (2021) - [i6]Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky:
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. CoRR abs/2107.10308 (2021) - [i5]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
MultPIM: Fast Stateful Multiplication for Processing-in-Memory. CoRR abs/2108.13378 (2021) - [i4]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
Making Memristive Processing-in-Memory Reliable. CoRR abs/2109.09687 (2021) - 2020
- [j11]Rotem Ben Hur, Ronny Ronen, Ameer Haj Ali, Debjyoti Bhattacharjee, Adi Eliahu, Natan Peled, Shahar Kvatinsky:
SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2434-2447 (2020) - [c18]Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky:
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. ICCAD 2020: 150:1-150:9 - [c17]Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky:
abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set Architecture. VLSI-SOC 2020: 28-33 - [c16]Natan Peled, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky:
X-MAGIC: Enhancing PIM Using Input Overwriting Capabilities. VLSI-SOC 2020: 64-69 - [c15]Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky:
abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory. VLSI-SoC (Selected Papers) 2020: 343-361 - [i3]Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky:
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. CoRR abs/2009.00881 (2020)
2010 – 2019
- 2019
- [j10]Nishil Talati, Heonjae Ha, Ben Perach, Ronny Ronen, Shahar Kvatinsky:
CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM. IEEE Micro 39(1): 33-43 (2019) - [i2]Kunal Korgaonkar, Ronny Ronen, Anupam Chattopadhyay, Shahar Kvatinsky:
The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm. CoRR abs/1910.10234 (2019) - 2018
- [j9]Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky:
Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing. IEEE Micro 38(5): 13-21 (2018) - [j8]Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky:
IMAGING: In-Memory AlGorithms for Image processiNG. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4258-4271 (2018) - [c14]Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
Practical challenges in delivering the promises of real processing-in-memory machines. DATE 2018: 1628-1633 - 2017
- [i1]Ronny Ronen:
Why & When Deep Learning Works: Looking Inside Deep Learnings. CoRR abs/1705.03921 (2017) - 2014
- [c13]Kenneth Czechowski, Victor W. Lee, Ed Grochowski, Ronny Ronen, Ronak Singhal, Richard W. Vuduc, Pradeep Dubey:
Improving the energy efficiency of Big Cores. ISCA 2014: 493-504 - 2010
- [e2]André Seznec, Uri C. Weiser, Ronny Ronen:
37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France. ACM 2010, ISBN 978-1-4503-0053-7 [contents]
2000 – 2009
- 2009
- [j7]Amit Golander, Shlomo Weiss, Ronny Ronen:
Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture. IEEE Trans. Circuits Syst. II Express Briefs 56-II(6): 474-478 (2009) - [c12]Ronny Ronen:
Larrabee: a many-core Intel architecture for visual computing. Conf. Computing Frontiers 2009: 225 - [c11]Shoumeng Yan, Xiaocheng Zhou, Ying Gao, Hu Chen, Sai Luo, Peinan Zhang, Naveen Cherukuri, Ronny Ronen, Bratin Saha:
Terascale chip multiprocessor memory hierarchy and programming model. HiPC 2009: 150-159 - [c10]Bratin Saha, Xiaocheng Zhou, Hu Chen, Ying Gao, Shoumeng Yan, Mohan Rajagopalan, Jesse Fang, Peinan Zhang, Ronny Ronen, Avi Mendelson:
Programming model for a heterogeneous x86 platform. PLDI 2009: 431-440 - 2008
- [j6]Amit Golander, Shlomo Weiss, Ronny Ronen:
DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals. IEEE Comput. Archit. Lett. 7(2): 65-68 (2008) - 2007
- [j5]Ronny Ronen, Antonio González:
Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences. IEEE Micro 27(1): 8-11 (2007) - 2004
- [c9]Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang:
Best of Both Latency and Throughput. ICCD 2004: 236-243 - 2003
- [j4]Aviad Cohen, Lev Finkelstein, Avi Mendelson, Ronny Ronen, Dmitry Rudoy:
On Estimating Optimal Performance of CPU Dynamic Thermal Management. IEEE Comput. Archit. Lett. 2 (2003) - [j3]Baruch Solomon, Avi Mendelson, Ronny Ronen, Doron Orenstein, Yoav Almog:
Micro-operation cache: a power aware frontend for variable instruction length ISA. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 801-811 (2003) - [c8]Roni Rosner, Micha Moffie, Yiannakis Sazeides, Ronny Ronen:
Selecting long atomic traces for high coverage. ICS 2003: 2-11 - 2001
- [j2]Ronny Ronen, Avi Mendelson, Konrad Lai, Shih-Lien Lu, Fred J. Pollack, John Paul Shen:
Coming challenges in microarchitecture and architecture. Proc. IEEE 89(3): 325-340 (2001) - [j1]Amir Roth, Ronny Ronen, Avi Mendelson:
Dynamic techniques for load and load-use scheduling. Proc. IEEE 89(11): 1621-1637 (2001) - [c7]Roni Rosner, Avi Mendelson, Ronny Ronen:
Filtering Techniques to Improve Trace-Cache Efficiency. IEEE PACT 2001: 37-48 - [c6]Baruch Solomon, Avi Mendelson, Doron Orenstein, Yoav Almog, Ronny Ronen:
Micro-operation cache: a power aware frontend for the variable instruction length ISA. ISLPED 2001: 4-9 - 2000
- [c5]Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen:
eXtended Block Cache. HPCA 2000: 61-70 - [c4]Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen:
Early load address resolution via register tracking. ISCA 2000: 306-315
1990 – 1999
- 1999
- [c3]Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan:
Speculation Techniques for Improving Load Related Instruction Scheduling. ISCA 1999: 42-53 - [c2]Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri C. Weiser:
Correlated Load-Address Predictors. ISCA 1999: 54-63 - [e1]Ronny Ronen, Matthew K. Farrens, Ilan Y. Spillinger:
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999. ACM/IEEE Computer Society 1999, ISBN 0-7695-0437-X [contents] - 1998
- [c1]Stéphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz:
A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification. MICRO 1998: 216-225
Coauthor Index
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