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CERN Document Server 2,034 record trovati  1 - 10successivofine  salta al record: La ricerca ha impiegato 0.45 secondi. 
1.
(100)
Characterization of a Low Power Gigabit Transceiver ASIC for High Energy Physics Experiments / Rasevic, Nikola
The high energy physics experiments developed at CERN for the High LuminosityLarge Hadron Collider (HL-LHC) are based on optical links that provide the clockdistribution and control towards the front-end electronics located in the experiments,and data transmission back from these electronics circuit [...]
CERN-THESIS-2020-258 - Novi Sad, Serbia : Faculty of Technical Sciences. - 39 p.

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2.
(91)
Development of an Optical Readout Hybrid for the CMS Outer Tracker Upgrade / Rasevic, Nikola (VINCA Inst. Nucl. Sci., Belgrade) ; Blanchot, Georges (CERN) ; Baron, S ; Kovacs, Mark Istvan (CERN) ; Kulis, S ; Porret, D ; Zografos, Angelos (Natl. Tech. U., Athens)
The pixel-strip modules for the CMS Tracker Phase-2 Upgrade for the HL-LHC integrate a readout hybrid (PS-ROH) for the control and data acquisition link. This hybrid is based on the new, low power and compact gigabit transceiver (LpGBT) and the versatile transceiver VTRx+ specifically designed for the upgrade. [...]
CMS-CR-2019-222.- Geneva : CERN, 2019 - 6 p. Fulltext: PDF;
In : TWEPP 2019 Topical Workshop on Electronics for Particle Physics, Santiago De Compostela, Spain, 2 - 6 Sep 2019
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Development of an Optical Readout Hybrid for the CMS Outer Tracker Upgrade / Rasevic, Nikola (Novi Sad U.) ; Blanchot, G (CERN) ; Baron, S (CERN) ; Kovacs, M (CERN) ; Kulis, S (CERN) ; Porret, D (CERN) ; Zografos, A (CERN) /CMS Collaboration
The pixel-strip modules for the CMS Tracker Phase-2 Upgrade for the HL-LHC integrate a readout hybrid (PS-ROH) for the control and data acquisition link. This hybrid is based on the new, low power and compact gigabit transceiver (LpGBT) and the versatile transceiver VTRx+ specifically designed for the upgrade. [...]
SISSA, 2020 - 5 p. - Published in : PoS TWEPP2019 (2020) 058 Fulltext: PDF;
In : TWEPP 2019 Topical Workshop on Electronics for Particle Physics, Santiago De Compostela, Spain, 2 - 6 Sep 2019, pp.058
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4.
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A Low-Cost, Low-Power Media Converter Solution for Next-Generation Detector Readout Systems / Perro, Alberto (CERN ; Marseille, CPPM) ; Vodnik, Mitja (CERN ; Stefan Inst., Ljubljana) ; Durante, Paolo (CERN)
High Energy Physics (HEP) data acquisition systems are often built from high-end FPGAs. As such systems scale in the HL-LHC era, severe under-utilization of FPGA transceivers can occur because front-end links prioritize radiation hardness and power consumption over raw data bandwidth. [...]
arXiv:2410.23173.- 2025-02-13 - 7 p. - Published in : JINST 20 (2025) C02027 Fulltext: 2410.23173 - PDF; document - PDF;
In : Topical Workshop on Electronics for Particle Physics 2024, Glasgow, United Kingdom, 30 Sep - 4 Oct 2024, pp.C02027
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The isolated USB programmer board for lpGBT configuration in ATLAS-HGTD upgrade / Han, L (Nanjing U.) ; Zhang, J (Beijing, Inst. High Energy Phys. ; Beijing, GUCAS) ; Liang, Z (Beijing, Inst. High Energy Phys.) ; Zhang, L (Nanjing U.) ; Qi, M (Nanjing U.) ; Chen, S (Nanjing U.) /ATLAS HGTD Collaboration
To configure the lpGBT chips that will be used on the peripheral electronics boards of the ATLAS-HGTD upgrade for the HL-LHC, a miniature and isolated USB programmer board for lpGBT (UPL) was developed based on an USB-protocol converter. Compared with the currently-used lpGBT programmer piGBT, the UPL has the advantages of compact profile, electrical isolation and cross-platform compatibility. [...]
2022 - 7 p. - Published in : JINST

In : TWEPP 2021 Topical Workshop on Electronics for Particle Physics, Online, Online, 20 - 24 Sep 2021, pp.C03030
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Hardware Design and Testing of the Generic Rear Transition Module for the Global Trigger Subsystem of ATLAS Phase-II Upgrade / Bonini, Filiberto (Brookhaven National Laboratory (US))
In the framework of the ATLAS experiment’s Phase-II Upgrade at the High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 $\mu s$-latency architecture. [...]
ATL-DAQ-PROC-2022-016. - 2023. - 7 p.
Original Communication (restricted to ATLAS) - Full text
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Hardware Design and Testing of the Generic Rear Transition Module for the Global Trigger Subsystem of ATLAS Phase-II Upgrade / Bonini, Filiberto (Brookhaven National Laboratory (US)) /ATLAS Collaboration
In the framework of the ATLAS experiment’s Phase-II Upgrade at the High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 $\mu s$-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. [...]
ATL-DAQ-SLIDE-2022-576.- Geneva : CERN, 2022 - 1 p. Fulltext: PDF; External link: Original Communication (restricted to ATLAS)
In : 2022 IEEE Nuclear Science Symposium (NSS), Medical Imaging Conference (MIC) and Room Temperature Semiconductor Detector (RTSD) Conference (NSS/MIC 2022), Milan, Italy, 5 - 12 Nov 2022
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Thumbnail
The lpGBT production testing system / Guettouche, Nour El Houda (speaker) (Centre National de la Recherche Scientifique (FR))
The Low-Power Gigabit Transceiver (lpGBT) is a radiation-tolerant ASIC designed to implement multipurpose high-speed bidirectional serial links in HEP experiments. Having more than 320 programmable registers, the ASIC is highly configurable. [...]
2021 - 1278. Conferences; TWEPP 2021 Topical Workshop on Electronics for Particle Physics External links: Talk details; Event details In : TWEPP 2021 Topical Workshop on Electronics for Particle Physics
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lpGBT: Low-Power Radiation-Hard Multipurpose High-Speed Transceiver ASIC for High-Energy Physics Experiments / Moreira, Paulo (CERN) ; Kulis, Szymon (CERN) ; Baron, Sophie (CERN) ; Biereigel, Stefan (CERN) ; Mendes, Eduardo Brandao De Souza (CERN) ; Matos-Carvalho, João P (New Lisbon U.) ; Faes, Bram (Leuven U.) ; Firlej, Miroslaw (AGH-UST, Cracow) ; Fiutowski, Tomasz (AGH-UST, Cracow) ; Fonseca, Jose (CERN) et al.
Commissioning of detector systems for the high-luminosity large Hadron collider (HL-LHC) is scheduled to take place between 2026 and 2028 at CERN. Application-specific integrated circuits (ASICs) for those systems have been in intense development over the past ten years. [...]
2025 - 14 p. - Published in : IEEE Trans. Nucl. Sci. 72 (2025) 24-37 Fulltext: PDF;
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10.
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A 2.56 GHz Radiation Hard Phase Locked Loop ASIC for High Speed Serial Communication Links / Prinzie, Jeffrey (Leuven U.) ; Steyaert, Michiel (Leuven U.) ; Leroux, Paul (Leuven U.) ; Moreira, Paulo (CERN)
This works presents the design and experimental study of a radiation hardened Phase Locked Loop (PLL) for high speed serial-communication links. These research results are used for the LpGBT (Low Power Gigabit Transceiver) chip which will be widely used for optical data-links between the detectors and the counting rooms in the HL LHC experiments. [...]
SISSA, 2018 - 6 p. - Published in : PoS TWEPP-17 (2017) 002 Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.002
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