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Time performance of Analog Pixel Test Structures with in-chip operational amplifier implemented in 65 nm CMOS imaging process
/ Rinella, Gianluca Aglieri (CERN) ; Aglietta, Luca (INFN, Turin ; Turin U.) ; Antonelli, Matias (INFN, Trieste) ; Barile, Francesco (INFN, Bari ; Bari U.) ; Benotto, Franco (INFN, Turin) ; Beolè, Stefania Maria (INFN, Turin ; Turin U.) ; Botta, Elena (INFN, Turin ; Turin U.) ; Bruno, Giuseppe Eugenio (Bari Polytechnic ; INFN, Bari) ; Carnesecchi, Francesca (CERN) ; Colella, Domenico (INFN, Bari ; Bari U.) et al.
In the context of the CERN EP R&D; on monolithic sensors and the ALICE ITS3 upgrade, the Tower Partners Semiconductor Co (TPSCo) 65 nm process has been qualified for use in high energy physics, and adopted for the ALICE ITS3 upgrade. An Analog Pixel Test Structure (APTS) featuring fast per pixel operational-amplifier-based buffering for a small matrix of four by four pixels, with a sensor with a small collection electrode and a very non-uniform electric field, was designed to allow detailed characterization of the pixel performance in this technology. [...]
arXiv:2407.18528.-
2024-11-12 - 27 p.
- Published in : Nucl. Instrum. Methods Phys. Res., A 1070 (2025) 170034
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Production and validation of industrially produced large-sized GEM foils for the Phase-2 upgrade of the CMS muon spectrometer
/ Abbas, Syed Mohsin (IPM, Tehran) ; Abbrescia, Marcello (INFN, Bari ; Bari U.) ; Abdalla, Hassan Fathy (Cairo, Acad. Sci. Res. Tech.) ; Abdelalim, Ahmed Ali (Cairo, Acad. Sci. Res. Tech.) ; Abuzeid Hassan, Shimaa Abdelwahed (INFN, Pavia) ; Aebi, Devin Michael (Texas A-M) ; Agapitos, Antonis (Peking U.) ; Ahmad, Ashfaq (Quaid-i-Azam U.) ; Ahmed, Asar (Delhi U.) ; Ahmed, Waqar (Quaid-i-Azam U.) et al.
The upgrade of the CMS detector for the high luminosity LHC (HL-LHC) will include gas electron multiplier (GEM) detectors in the end-cap muon spectrometer.
Due to the limited supply of large area GEM detectors, the Korean CMS (KCMS) collaboration had formed a consortium with Mecaro Co., Ltd. to serve as a supplier of GEM foils with area of approximately 0.6 m$^{2}$.
The consortium has developed a double-mask etching technique for production of these large-sized GEM foils.
This article describes the production, quality control, and quality assessment (QA/QC) procedures and the mass production status for the GEM foils. [...]
CMS-NOTE-2023-006; CERN-CMS-NOTE-2023-006.-
Geneva : CERN, 2023 - 18 p.
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Quality Control of Mass-Produced GEM Detectors for the CMS GE1/1 Muon Upgrade
/ Abbas, Syed Mohsin (IPM, Tehran) ; Abbrescia, Marcello (INFN, Bari ; Bari U.) ; Abdalla, Hassan Fathy (Cairo, Acad. Sci. Res. Tech.) ; Abdelalim, Ahmed Ali (Cairo, Acad. Sci. Res. Tech.) ; Abuzeid Hassan, Shimaa Abdelwahed (INFN, Pavia) ; Agapitos, Antonis (Peking U.) ; Ahmad, Ashfaq (Quaid-i-Azam U.) ; Ahmed, Asar (Delhi U.) ; Ahmed, Waqar (Quaid-i-Azam U.) ; Aimè, Chiara (INFN, Pavia ; Pavia U.) et al.
The series of upgrades to the Large Hadron Collider, culminating in the High Luminosity Large Hadron Collider, will enable a significant expansion of the physics program of the CMS experiment. However, the accelerator upgrades will also make the experimental conditions more challenging, with implications for detector operations, triggering, and data analysis. [...]
CMS-NOTE-2022-004; CERN-CMS-NOTE-2022-004.-
Geneva : CERN, 2022 - 47 p.
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Results from CHIPIX-FE0, a small-scale prototype of a new generation pixel readout ASIC in 65 nm CMOS for HL-LHC
/ Pacher, Luca (INFN, Turin) ; Monteil, Ennio (INFN, Turin) ; Paternò, Andrea (INFN, Turin ; Polytech. Turin) ; Panati, Serena (INFN, Turin ; Polytech. Turin) ; Demaria, Natale (INFN, Turin) ; Rivetti, Angelo (INFN, Turin) ; Da Rocha Rolo, Manuel Dionisio (INFN, Turin) ; Dellacasa, Giulio (INFN, Turin) ; Mazza, Giovanni (INFN, Turin) ; Rotondo, Francesco (INFN, Turin) et al.
A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 x 64 pixels with 50 $\mu$m x 50 $\mu$m pixel size embedding two different architectures of analog front-ends working in parallel. [...]
SISSA, 2017 - 5 p.
- Published in : PoS TWEPP-17 (2017) 024
Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.024
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Development of a large pixel chip demonstrator in RD53 for ATLAS and CMS upgrades
/ Conti, Elia (CERN) ; Barbero, Marlon (Marseille, CPPM) ; Fougeron, Denis (Marseille, CPPM) ; Godiot, Stephanie (Marseille, CPPM) ; Menouni, Mohsine (Marseille, CPPM) ; Pangaud, Patrick (Marseille, CPPM) ; Rozanov, Alexandre (Marseille, CPPM) ; Breugnon, Patrick (Marseille, CPPM) ; Bomben, Marco (Paris U., VI-VII) ; Calderini, Giovanni (Paris U., VI-VII) et al.
/RD53
RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes. [...]
SISSA, 2017 - 5 p.
- Published in : PoS TWEPP-17 (2017) 005
Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.005
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