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1.
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Digital duty-cycle correction circuit for clock paths in radiation-tolerant high-speed wireline transmitters
/ Klekotko, A (Leuven U. ; CERN) ; Baszczyk, M (CERN) ; Biereigel, S (CERN) ; Kulis, S (CERN) ; Martina, F (CERN) ; Moreira, P (CERN) ; Tavernier, F (Leuven U.) ; Prinzie, J (Leuven U.)
Ongoing developments in the field of radiation-toleranthigh-speed transmitters (HSTs)aim at increasing thedata rates above 25 Gb/s while increasingtotal ionizing dose (TID)tolerance above 1 Grad. The use of half-ratearchitectures imposes tight constraints on clock signal quality, in particular itsduty-cycle. [...]
2024 - 7 p.
- Published in : JINST 19 (2024) C02030
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2023 (TWEPP 2023), Geremeas, Sardinia, Italy, 1 - 6 Oct 2023, pp.C02030
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2.
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Radiation hard true single-phase-clock logic for high-speed circuits in 28 nm CMOS
/ Klekotko, A (Leuven U. ; CERN) ; Baszczyk, M (CERN) ; Biereigel, S (Leuven U. ; CERN) ; Kulis, S (CERN) ; Moreira, P (CERN) ; Prinzie, J (Leuven U.) ; Tavernier, F (Leuven U.)
True Single-Phase-Clock (TSPC) dynamic logic is widely used in high-speed circuits such as high-speed SERDES (Serializer/Deserializer) and frequency dividers. TSPC flip-flops (FF) are known for their high operational speed and low power consumption, compared to static FFs. [...]
2023 - 8 p.
- Published in : JINST 18 (2023) C02068
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2022 (TWEPP 2022), Bergen, Norway, 19 - 23 Sep 2022, pp.C02068
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3.
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4.
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VFAT3: A Trigger and Tracking Front-end ASIC for the Binary Readout of Gaseous and Silicon Sensors
/ Aspell, P (CERN) ; Bravo, C (UCLA) ; Dabrowski, M (Brookhaven) ; De Lentdecker, G (Brussels U.) ; De Robertis, G (INFN, Bari) ; Firlej, M (AGH-UST, Cracow) ; Fiutowski, T (AGH-UST, Cracow) ; Hakkarainen, T (Lappeenranta U. Tech.) ; Idzik, M (AGH-UST, Cracow) ; Irshad, A (CERN ; Brussels U.) et al.
VFAT3 is the front-end ASIC designed specifically for the readout of GEM detectors within the CMS experiment during the high luminosity phase of the LHC at CERN. This paper presents the analog and digital design plus the measured functional and characterization results. [...]
2019 - 8 p.
- Published in : 10.1109/NSSMIC.2018.8824655
In : 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC 2018), Sydney, Australia, 10 - 17 Nov 2018, pp.8824655
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5.
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Low-noise and low-power front-end in 130 nm CMOS for triple-GEM detectors supporting wide range of detector capacitances with gain and peaking time programmability.
/ Dabrowski, M (CERN) ; Aspell, P (CERN) ; Bravo, C (UCLA, Los Angeles (main)) ; De Lentdecker, G (U. Brussels (main)) ; De Robertis, G (INFN, Bari) ; Irshad, A (CERN ; Unlisted, PK) ; Licciulli, F (INFN, Bari) ; Loddo, F (INFN, Bari) ; Petrow, H (Lappeenranta U. Tech.) ; Rosa, J (U. Brussels (main)) et al.
An analog front-end in 130 (nm) CMOS technology was developed for the readout of triple-GEM detectors in the CMS experiment at CERN. The front-end has programmable peaking time - 15, 25, 35 and 45 (ns) - and gain - 48, 16.4 and 8.6 (mV/fC) - and is able to support a detector capacitance ranging from 0 to 120 (pF). [...]
2018 - 3 p.
- Published in : 10.1109/NSSMIC.2017.8532666
In : 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC 2017), Atlanta, Georgia, USA, 21 - 28 Oct 2017, pp.8532666
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6.
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A Verification Platform to provide the Functional, Characterization and Production testing for the VFAT3 ASIC
/ Petrow, H (Lappeenranta U. Tech.) ; Aspell, P (CERN) ; Bravo, C (UCLA, Los Angeles (main)) ; Dabrowski, M (CERN) ; De Lentdecker, G (U. Brussels (main)) ; Leroux, P (Leuven U.) ; De Robertis, G (INFN, Bari) ; Irshad, A (Unlisted, PK) ; Lenzi, T (U. Brussels (main)) ; Licciulli, F (INFN, Bari) et al.
VFAT3 is a front-end ASIC designed for the readout of GEM detectors in the CMS Muon system. The strategy for the chip design was to design the full chip at once but provide extensive test and debug facilities for individual characterization of each internal chip module. [...]
2018 - 3 p.
- Published in : 10.1109/NSSMIC.2017.8532822
In : 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC 2017), Atlanta, Georgia, USA, 21 - 28 Oct 2017, pp.8532822
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7.
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Operational Experience With the GEM Detector Assembly Lines for the CMS Forward Muon Upgrade
/ Abbaneo, D (CERN) ; Abbrescia, M (Bari Polytechnic ; INFN, Bari) ; Ahmad, A (NCP, Islamabad) ; Ahmed, W (NCP, Islamabad) ; Ali, C (Texas A-M) ; Altieri, P R (Bari Polytechnic ; INFN, Bari) ; Amr, M (Cairo, Acad. Sci. Res. Tech.) ; Asghar, I (NCP, Islamabad) ; Aspell, P (CERN) ; Assran, Y (Cairo, Acad. Sci. Res. Tech.) et al.
The CMS Collaboration has been developing large-area triple-gas electron multiplier (GEM) detectors to be installed in the muon Endcap regions of the CMS experiment in 2019 to maintain forward muon trigger and tracking performance at the High-Luminosity upgrade of the Large Hadron Collider (LHC); 10 preproduction detectors were built at CERN to commission the first assembly line and the quality controls (QCs). These were installed in the CMS detector in early 2017 and participated in the 2017 LHC run. [...]
2018 - 9 p.
- Published in : IEEE Trans. Nucl. Sci. 65 (2018) 2808-2816
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8.
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9.
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GBLD10+: a compact low-power 10 Gb/s VCSEL driver
/ Zhang, T (Southern Methodist U.) ; Kulis, S (CERN) ; Gui, P (Southern Methodist U.) ; Tavernier, F (Leuven U.) ; Moreira, P (CERN)
We report the design and implementation of the GBLD10+, a low-power 10 Gb/s VCSEL driver for High Energy Physics (HEP) applications. With new circuit techniques, the driver consumes only 31 mW and occupies a small area of 400 μm × 1750 μm including the IO PADs and sealrings. [...]
2016
- Published in : JINST 11 (2016) C01015
IOP Open Access article: PDF;
In : Topical Workshop on Electronics for Particle Physics, Lisbon, Portugal, 28 Sep - 2 Oct 2015, pp.C01015
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10.
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The eCDR-PLL, a radiation-tolerant ASIC for clock and data recovery and deterministic phase clock synthesis
/ Leitao, P (CERN) ; Francisco, R (CERN) ; Llopart, X (CERN) ; Tavernier, F (Leuven U.) ; Baron, S (CERN) ; Bonacini, S (CERN) ; Moreira, P (CERN)
A radiation-tolerant CDR/PLL ASIC has been developed for the upcoming LHC upgrades, featuring clock Frequency Multiplication (FM) and Clock and Data Recovery (CDR), showing deterministic phase and low jitter. Two FM modes have been implemented: either generating 40, 60, 120 and 240 MHz clock outputs for GBT-FPGA applications or providing 40, 80, 160 and 320 MHz clocks for TTC and e-link applications. [...]
2015
- Published in : JINST 10 (2015) C03024
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2014, Aix En Provence, France, 22 - 26 Sep 2014, pp.C03024
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