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1.
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RD53 pixel chips for the ATLAS and CMS Phase-2 upgrades at HL-LHC
/ Loddo, F (INFN, Bari) ; Andreazza, A (Milan U. ; INFN, Milan) ; Arteche, F (Sao Paulo, Inst. Tech. Aeronautics) ; Barbero, M B (Marseille, CPPM) ; Barillon, P (Marseille, CPPM) ; Beccherle, R (INFN, Pisa) ; Bilei, G M (INFN, Perugia ; Perugia U.) ; Bjalas, W (CERN) ; Bonaldo, S (INFN, Padua ; Padua U.) ; Bortoletto, D (Oxford U.) et al.
The Phase-2 upgrades at the High-Luminosity LHC of ATLAS and CMS experiments at CERN will require a new tracker with readout electronics operating in extremely harsh radiation environment (1 Grad), high hit rate (3.5 GHz/cm2) and high data rate readout (5 Gb/s). The RD53 collaboration is a joint effort between the ATLAS and CMS to qualify the chosen 65 nm CMOS technology in high radiation environment and develop the pixel readout chips of both experiments. [...]
FERMILAB-PUB-24-0469-PPD.-
2024 - 5 p.
- Published in : Nucl. Instrum. Methods Phys. Res., A 1067 (2024) 169682
In : PSD13: The 13th International Conference on Position Sensitive Detectors, Oxford, United Kingdom, 3 - 9 Sep 2023, pp.169682
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2.
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3.
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4.
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Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC
/ Marconi, S (Marseille, CPPM) ; Barbero, M B (Marseille, CPPM) ; Fougeron, D (Marseille, CPPM) ; Godiot, S (Marseille, CPPM) ; Menouni, M (Marseille, CPPM) ; Pangaud, P (Marseille, CPPM) ; Rozanov, A (Marseille, CPPM) ; Breugnon, P (Marseille, CPPM) ; Bomben, M (Paris U., VI-VII) ; Calderini, G (Paris U., VI-VII) et al.
The RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, in order to face the unprecedented design requirements of the pixel 2 phase upgrades of the CMS and ATLAS experiments at CERN. This prototype chip is designed to demonstrate that a set of challenging specifications can be met, such as: high granularity (small pixels of 50×50 or 25× 100 µm2) and large pixel chip size (~2x2 cm2), high hit rate (3 GHz/cm2), high readout speed, very high radiation levels (500 Mrad - 1 Grad) and operation with serial powering. [...]
2019 - 4 p.
- Published in : 10.1109/NSSMIC.2018.8824486
In : 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC 2018), Sydney, Australia, 10 - 17 Nov 2018, pp.8824486
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5.
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A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC
/ Pacher, L. (Università di Torino and INFN Sezione di Torino) ; Monteil, E (Università di Torino and INFN Sezione di Torino) ; Paternò, A (Politecnico di Torino and INFN Sezione di Torino) ; Panati, S (Politecnico di Torino and INFN Sezione di Torino) ; Demaria, L (INFN Sezione di Torino) ; Rivetti, A (INFN Sezione di Torino) ; Da Rocha Rolo, M (INFN Sezione di Torino) ; Dellacasa, G (INFN Sezione di Torino) ; Mazza, G (INFN Sezione di Torino) ; Rotondo, F (INFN Sezione di Torino) et al.
The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments.
This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS.
The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. [...]
AIDA-2020-CONF-2018-011.-
Geneva : CERN, 2018
- Published in : PoS Vertex2016 (2017) 054
Fulltext: PDF;
In : VERTEX 2016, La Biodola, Italy, 25 - 30 Sep 2016, pp.054
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6.
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Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC
/ Pacher, L. (INFN Sezione di Torino, Torino, Italy) ; Monteil, E. (INFN Sezione di Torino, Torino, Italy) ; Demaria, N. (INFN Sezione di Torino, Torino, Italy) ; Rivetti, A. (INFN Sezione di Torino, Torino, Italy) ; Da Rocha Rolo, M. (INFN Sezione di Torino, Torino, Italy) ; Dellacasa, G. (INFN Sezione di Torino, Torino, Italy) ; Mazza, G. (INFN Sezione di Torino, Torino, Italy) ; Rotondo, F. (INFN Sezione di Torino, Torino, Italy) ; Wheadon, R. (INFN Sezione di Torino, Torino, Italy) ; Paternò, A. (Politecnico di Torino and INFN Sezione di Torino, Torino, Italy) et al.
A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 × 64 pixels with 50 μm × 50 μm pixel size embedding two different architectures of analog front-ends working in parallel. [...]
AIDA-2020-CONF-2018-004.-
Geneva : CERN, 2018
- Published in : Proceedings of Science
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017
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7.
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Results from CHIPIX-FE0, a small-scale prototype of a new generation pixel readout ASIC in 65 nm CMOS for HL-LHC
/ Pacher, Luca (INFN, Turin) ; Monteil, Ennio (INFN, Turin) ; Paternò, Andrea (INFN, Turin ; Polytech. Turin) ; Panati, Serena (INFN, Turin ; Polytech. Turin) ; Demaria, Natale (INFN, Turin) ; Rivetti, Angelo (INFN, Turin) ; Da Rocha Rolo, Manuel Dionisio (INFN, Turin) ; Dellacasa, Giulio (INFN, Turin) ; Mazza, Giovanni (INFN, Turin) ; Rotondo, Francesco (INFN, Turin) et al.
A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 x 64 pixels with 50 $\mu$m x 50 $\mu$m pixel size embedding two different architectures of analog front-ends working in parallel. [...]
SISSA, 2017 - 5 p.
- Published in : PoS TWEPP-17 (2017) 024
Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.024
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8.
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Development of a large pixel chip demonstrator in RD53 for ATLAS and CMS upgrades
/ Conti, Elia (CERN) ; Barbero, Marlon (Marseille, CPPM) ; Fougeron, Denis (Marseille, CPPM) ; Godiot, Stephanie (Marseille, CPPM) ; Menouni, Mohsine (Marseille, CPPM) ; Pangaud, Patrick (Marseille, CPPM) ; Rozanov, Alexandre (Marseille, CPPM) ; Breugnon, Patrick (Marseille, CPPM) ; Bomben, Marco (Paris U., VI-VII) ; Calderini, Giovanni (Paris U., VI-VII) et al.
/RD53
RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes. [...]
SISSA, 2017 - 5 p.
- Published in : PoS TWEPP-17 (2017) 005
Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.005
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9.
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Design of analog front-ends for the RD53 demonstrator chip
/ Gaioni, L (Bergamo U. ; INFN, Pavia) ; De Canio, F (Bergamo U. ; INFN, Pavia) ; Nodari, B (Bergamo U. ; INFN, Pavia) ; Manghisoni, M (Bergamo U. ; INFN, Pavia) ; Re, V (Bergamo U. ; INFN, Pavia) ; Traversi, G (Bergamo U. ; INFN, Pavia) ; Barbero, M B (Marseille, CPPM) ; Fougeron, D (Marseille, CPPM) ; Gensolen, F (Marseille, CPPM) ; Godiot, S (Marseille, CPPM) et al.
The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. [...]
SISSA, 2017 - 14 p.
- Published in : PoS Vertex 2016 (2017) 036
Fulltext: PDF; External link: PoS server
In : VERTEX 2016, La Biodola, Italy, 25 - 30 Sep 2016, pp.036
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10.
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A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC
/ Paternò, Andrea (INFN, Turin ; Turin Polytechnic) ; Pacher, L (Turin U. ; INFN, Turin) ; Monteil, E (Turin U. ; INFN, Turin) ; Loddo, F (INFN, Bari) ; Demaria, N (INFN, Turin) ; Gaioni, L (INFN, Pavia ; Bergamo U., Ingengneria Dept.) ; Canio, F De (INFN, Pavia ; Pavia U.) ; Traversi, G (INFN, Pavia ; Bergamo U., Ingengneria Dept.) ; Re, V (INFN, Pavia ; Bergamo U., Ingengneria Dept.) ; Ratti, L (INFN, Pavia ; Pavia U.) et al.
This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of $50×50μm^{2}$ pixels is realised. [...]
2017 - 12 p.
- Published in : JINST 12 (2017) C02043
In : Topical Workshop on Electronics for Particle Physics, Karlsruhe, Germany, 26 - 30 Sep 2016, pp.C02043
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