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1.
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An Improved Algorithm for On-Chip Clustering and Lossless Data Compression of HL-LHC Pixel Hits
/ Baruffa, Giuseppe (Perugia U.) ; Placidi, Pisana (INFN, Perugia ; Perugia U.) ; Di Salvo, Andrea (INFN, Turin ; Polytech. Turin) ; Marconi, Sara (CERN) ; Paternò, Andrea (INFN, Turin ; Polytech. Turin)
A prototype chip, called RD53A, has been designed by the RD53 collaboration to face the very high hit and trigger rate requirements (up to 3 GHz/cm$^2$ and 1 MHz, respectively) of the High Luminosity LHC experiment upgrades. In this paper, an improved algorithm for data compression, capable of sustaining the very high data volume and proposed to be implemented in the periphery of the chip, is presented: it exploits Run Length Encoding (RLE) and Variable Length Coding (VLC) to compact chip pixel hit patterns. [...]
2019 - 5 p.
- Published in : 10.1109/NSSMIC.2018.8824281
In : 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC 2018), Sydney, Australia, 10 - 17 Nov 2018, pp.8824281
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2.
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A UVM simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips
/ Marconi, Sara (CERN ; Perugia U. ; INFN, Perugia) ; Conti, E (CERN) ; Christiansen, J (CERN) ; Placidi, P (Perugia U. ; INFN, Perugia)
The operating conditions of the High Luminosity upgrade of the Large Hadron Collider are very demanding for the design of next generation hybrid pixel readout chips in terms of particle rate, radiation level and data bandwidth. To this purpose, the RD53 Collaboration has developed for the ATLAS and CMS experiments a dedicated simulation and verification environment using industry-consolidated tools and methodologies, such as SystemVerilog and the Universal Verification Methodology (UVM). [...]
2018 - 14 p.
- Published in : JINST 13 (2018) P05018
Fulltext from publisher: pdf - PDF; 10.1088_1748-0221_13_05_P05018 - PDF;
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3.
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Fulltext
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4.
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5.
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Performance evaluation of digital pixel readout chip architecture operating at very high rate through a reusable UVM simulation framework
/ Conti, Elia (CERN) ; Marconi, Sara (CERN ; U. Perugia (main) ; INFN, Perugia) ; Hemperek, Tomasz (Bonn U.) ; Christiansen, J⊘rgen (CERN) ; Placidi, Pisana (INFN, Perugia ; Perugia U.)
A large scale demonstrator pixel readout chip is currently being designed by the RD53 Collaboration, with the goal of proving the suitability of 65 nm technology for the extreme operating conditions associated to the High Luminosity upgrades of the ATLAS and CMS experiments at the Large Hadron Collider. The VEPIX53 simulation and verification environment was developed in order to support the chip design flow at different steps, from architectural modeling and optimization to final design verification, thanks to the flexibility and reusability of System Verilog and the Universal Verification Methodology (UVM) library. [...]
2017 - 4 p.
- Published in : 10.1109/NSSMIC.2016.8069646
In : IEEE Nuclear Science Symposium and Medical Imaging Conference, Strasbourg, France, 29 Oct - 6 Nov 2016, pp.8069646
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6.
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A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications
/ Marconi, Sara (Perugia U. ; INFN, Perugia ; CERN) ; Conti, Elia (CERN) ; Placidi, Pisana (Perugia U. ; INFN, Perugia) ; Scorzoni, Andrea (Perugia U. ; INFN, Perugia) ; Christiansen, Jorgen (CERN) ; Hemperek, Tomasz (Bonn U.)
The adoption of a system-level simulation environment based on standard methodologies is a valuable solution to handle system complexity and achieve best design optimization. This work is focused on the implementation of such a platform for High Energy Physics (HEP) applications, i.e. [...]
2017 - 7 p.
- Published in : 10.1007/978-3-319-47913-2_5
In : 2015 Applications in Electronics Pervading Industry, Environment and Society Conference, Rome, Italy, 5 - 6 May 2015, pp.35-41
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7.
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Low-power optimisation of a pixel array architecture for next generation High Energy Physics detectors
/ Marconi, Sara (U. Perugia (main) ; INFN, Italy) ; Hemperek, Tomasz (Bonn U.) ; Placidi, Pisana (U. Perugia (main) ; INFN, Italy) ; Scorzoni, Andrea (U. Perugia (main) ; INFN, Italy) ; Conti, Elia (CERN) ; Christiansen, Jorgen (CERN)
A large scale pixel readout chip is being designed by the RD53 Collaboration, in order to prove the suitability of 65 nm technology for the extreme operating conditions foreseen for the High Luminosity upgrades of the ATLAS and CMS experiments at CERN. The use of advanced digital design and simulation tools is essential to guide architectural and implementation choices for the design and optimisation of pixel chips which will be powered from a serial powering scheme. [...]
2017 - 4 p.
- Published in : 10.1109/PRIME.2017.7974142
In : 13th Conference on PhD Research in Microelectronics and Electronics, Taormina, Italy, 12 - 15 Jun 2017, pp.201-204
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8.
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Results from CHIPIX-FE0, a small-scale prototype of a new generation pixel readout ASIC in 65 nm CMOS for HL-LHC
/ Pacher, Luca (INFN, Turin) ; Monteil, Ennio (INFN, Turin) ; Paternò, Andrea (INFN, Turin ; Polytech. Turin) ; Panati, Serena (INFN, Turin ; Polytech. Turin) ; Demaria, Natale (INFN, Turin) ; Rivetti, Angelo (INFN, Turin) ; Da Rocha Rolo, Manuel Dionisio (INFN, Turin) ; Dellacasa, Giulio (INFN, Turin) ; Mazza, Giovanni (INFN, Turin) ; Rotondo, Francesco (INFN, Turin) et al.
A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 x 64 pixels with 50 $\mu$m x 50 $\mu$m pixel size embedding two different architectures of analog front-ends working in parallel. [...]
SISSA, 2017 - 5 p.
- Published in : PoS TWEPP-17 (2017) 024
Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.024
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9.
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Development of a large pixel chip demonstrator in RD53 for ATLAS and CMS upgrades
/ Conti, Elia (CERN) ; Barbero, Marlon (Marseille, CPPM) ; Fougeron, Denis (Marseille, CPPM) ; Godiot, Stephanie (Marseille, CPPM) ; Menouni, Mohsine (Marseille, CPPM) ; Pangaud, Patrick (Marseille, CPPM) ; Rozanov, Alexandre (Marseille, CPPM) ; Breugnon, Patrick (Marseille, CPPM) ; Bomben, Marco (Paris U., VI-VII) ; Calderini, Giovanni (Paris U., VI-VII) et al.
/RD53
RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes. [...]
SISSA, 2017 - 5 p.
- Published in : PoS TWEPP-17 (2017) 005
Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.005
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10.
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Serial powering optimization for CMS and ATLAS pixel detectors within RD53 collaboration for HL-LHC: system level simulations and testing
/ Orfanelli, Stella (CERN) ; Christiansen, Jorgen (CERN) ; Hamer, Matthias (U. Bonn (main)) ; Hinterkeuser, F (U. Bonn (main)) ; Karagounis, M (FH Dortmund) ; Pradas Luengo, Alvaro (Zaragoza, ITA) ; Marconi, Sara (INFN, Perugia ; Perugia U. ; CERN) ; Ruini, Daniele (Zurich, ETH)
Serial powering is the baseline choice for low mass power distribution for the CMS and ATLAS HL-LHC pixel detectors. Two 2.0 A Shunt-LDO regulators are integrated in a prototype pixel chip implemented in 65-nm CMOS technology and used to provide constant supply voltages to its power domains from a constant input current. [...]
CMS-CR-2017-385.-
Geneva : CERN, 2017 - 5 p.
- Published in : PoS TWEPP-17 (2017) 055
Fulltext: PDF; External link: PoS Server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.055
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