CERN Accelerating science

Article
Report number	SLAC-PUB-11753
Title	PEP-II Transverse Feedback Electronics Upgrade
Author(s)	Weber, Jonah ; Akre, Ron ; Chin, Michael ; Doolittle, Lawrence
Affiliation	(LBNL, Berkeley) ; (SLAC)
Publication	2005
Imprint	May 2005
Number of pages	3
In:	21st IEEE Particle Accelerator Conference, Knoxville, TN, USA, 16 - 20 May 2005, pp.3928
Subject category	Accelerators and Storage Rings
Abstract	The PEP-II B Factory at the Stanford Linear Accelerator Center (SLAC) requires an upgrade of the transverse feedback system electronics. The new electronics require 12-bit resolution and a minimum sampling rate of 238 Msps. A Field Programmable Gate Array (FPGA) is used to implement the feedback algorithm. The FPGA also contains an embedded PowerPC 405 (PPC-405) processor to run control system interface software for data retrieval, diagnostics, and system monitoring. The design of this system is based on the Xilinx® ML300 Development Platform, a circuit board set containing an FPGA with an embedded processor, a large memory bank, and other peripherals. This paper discusses the design of a digital feedback system based on an FPGA with an embedded processor. Discussion will include specifications, component selection, and integration with the ML300 design.