Author(s)
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Dobrijević, D (CERN ; Zagreb U.) ; Allport, P (Birmingham U.) ; Asensi, I (CERN) ; Berlea, D (DESY, Zeuthen) ; Bortoletto, D (Oxford U.) ; Buttar, C (Glasgow U.) ; Dachs, F (CERN) ; Dao, V (CERN) ; Denizli, H (Abant Izzet Baysal U.) ; Sanz de Acedo, L F (CERN) ; Gabrielli, A (CERN) ; Gonella, L (Birmingham U.) ; González, V (Valencia U.) ; LeBlanc, M (CERN) ; Núñez, M V (CERN ; Valencia U.) ; Oyulmaz, K (Abant Izzet Baysal U.) ; Pernegger, H (CERN) ; Piro, F (CERN ; Ecole Polytechnique, Lausanne) ; Riedler, P (CERN) ; Sandaker, H (Darmstadt, Tech. U.) ; Sánchez, C S (CERN) ; Snoeys, W (CERN) ; Suligoj, T (Zagreb U.) ; van Rijnbach, M (CERN ; Oslo U.) ; Weick, J (CERN ; Darmstadt, Tech. U.) ; Worm, S (DESY, Zeuthen) |
Abstract
| The planned MALTA3 DMAPS designed in the standard TowerJazz 180 nm imaging process will implement the numerous process modifications, as well as front-end changes in order to boost the charge collection efficiency after the targeted fluence of 1 × 10$^{15}$ 1 MeV n$_{eq}$/cm$^{2}$. The effectiveness of these changes have been demonstrated with recent measurements of the full size MALTA2 chip. With the original MALTA concept being fully asynchronous, a small-scale MiniMALTA demonstrator chip has been developed with the intention of bridging the gap between the asynchronous pixel matrix, and the synchronous DAQ. This readout architecture will serve as a baseline for MALTA3, with focus on improved timing performance. The synchronization memory has been upgraded to allow clock speeds of up to 1.28 GHz, with the goal of achieving a sub-nanosecond on-chip timing resolution. The subsequent digital readout chain has been modified and will be discussed in the context of the overall sensor architecture. |