| Article | |
| Title | Digital duty-cycle correction circuit for clock paths in radiation-tolerant high-speed wireline transmitters |
| Author(s) | Klekotko, A (Leuven U. ; CERN) ; Baszczyk, M (CERN) ; Biereigel, S (CERN) ; Kulis, S (CERN) ; Martina, F (CERN) ; Moreira, P (CERN) ; Tavernier, F (Leuven U.) ; Prinzie, J (Leuven U.) |
| Publication | 2024 |
| Number of pages | 7 |
| In: | JINST 19 (2024) C02030 |
| In: | Topical Workshop on Electronics for Particle Physics 2023 (TWEPP 2023), Geremeas, Sardinia, Italy, 1 - 6 Oct 2023, pp.C02030 |
| DOI | 10.1088/1748-0221/19/02/C02030 |
| Subject category | Detectors and Experimental Techniques |
| Abstract | Ongoing developments in the field of radiation-toleranthigh-speed transmitters (HSTs)aim at increasing thedata rates above 25 Gb/s while increasingtotal ionizing dose (TID)tolerance above 1 Grad. The use of half-ratearchitectures imposes tight constraints on clock signal quality, in particular itsduty-cycle. Radiation degradation of transistors in the clock path causesduty cycle distortion (DCD), affecting theoutput signal quality of the HST. In this paper, a digitally controlled duty-cyclecorrection circuit suitable for HST is presented. It compensates forprocess voltage temperature (PVT)variations as wellas radiation-induced duty-cycle distortion of the clock. |
| Copyright/License | publication: © 2024 The Author(s) (License: CC-BY-4.0) |
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Record created 2024-08-01, last modified 2024-09-06
