| ATLAS Note | |
| Report number | ATL-DAQ-PROC-2024-007 |
| Title | Phase-II Upgrade of the ATLAS L1 Central Trigger |
| Author(s) |
Koulouris, Aimilianos (CERN) ; Axiotis, Konstantinos (Universite de Geneve (CH)) ; Bonini, Filiberto (CERN) ; Haas, Stefan Ludwig (CERN) ; Kulinska, Anna Malgorzata (CERN) ; Marsella, Luca (Politecnico di Milano (IT)) ; Marzin, Antoine (CERN) ; Pauly, Thilo (CERN) ; Penc, Ondrej (CERN) ; Ryjov, Vladimir (CERN) ; Sanfilippo, Lorenzo (Heidelberg University (DE)) ; Simoniello, Rosa (CERN) ; Spiwoks, Ralf (CERN) ; Vichoudis, Paschalis (CERN) ; Wengler, Thorsten (CERN) |
| Corporate Author(s) | The ATLAS collaboration |
| Publication | 2024 |
| Imprint | 31 Jul 2024 |
| Number of pages | 5 |
| In: | 22nd International Workshop on Advanced Computing and Analysis Techniques in Physics Research, Stony Brook, United States, 11 - 15 Mar 2024 |
| Subject category | Particle Physics - Experiment |
| Accelerator/Facility, Experiment | CERN LHC ; ATLAS |
| Abstract | The ATLAS trigger system will be upgraded for the Phase-II period of LHC operation, with data-taking expected in 2029. This system will include a Level-0 trigger based on custom electronics and firmware, and a high-level software trigger running on off-the-shelf hardware. The upgraded L0 trigger system uses information from the calorimeters and the muon trigger detectors. The system will be operating at ten times the current rate, reaching 1MHz readout rate. The MUCTPI receives candidates from muon trigger sectors and calculates multiplicities. Muon multiplicity information is sent to the Central-Trigger-Processor and trigger objects are sent to the L0 Global Trigger Processor. In Phase-II, the CTP will be a newly designed and custom-built electronics system, based on the ATCA standard. It will employ a SoC and optical serial inputs to receive trigger information from the Global Trigger and the MUCTPI system. The control and monitoring software will run directly on the SoC, while the trigger logic runs on an FPGA. The CTP will need to allow a set of 1024 trigger items based on 1024 usable single-bit inputs, requiring updates in the trigger logic implementation, as well as the software for compiling the trigger conditions into FPGA configuration files. New features will also be introduced, such as delayed triggers. We will present the design and status of the Phase-II L0CT system and its new features, including a view of the pilot Phase-I upgrade, which paves the way for the upcoming upgrades. |
Записът е създаден на 2024-07-31, последна промяна на 2024-08-01
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