Elsevier B.V. : Rate-capability of the VMM3a front-end in the RD51 Scalable Readout System

Pfeiffer, D.; Iakovidis, G.; Lupberger, M.; Christensen, M.J.; Flöthner, K.; van Stenis, M.; Garcia, F.; Muller, H.; Oliveri, E.; Janssens, D.; Desch, K.; Samarati, J.; Utrobicic, A.; Brunbauer, F.; Alcock, S.; Veenhof, R.; Hracek, M.; Hall-Wilton, R.; Rusu, A.; Schwäbig, P.; Ropelewski, L.; Scharenberg, L.; Kaminski, J.

doi:10.1016/j.nima.2022.166548

Article
Report number	arXiv:2109.10287
Title	Rate-capability of the VMM3a front-end in the RD51 Scalable Readout System
Author(s)	Pfeiffer, D. (ESS, Lund ; CERN ; Milan Bicocca U.) ; Scharenberg, L. (CERN ; Bonn U.) ; Schwäbig, P. (Bonn U.) ; Alcock, S. (ESS, Lund) ; Brunbauer, F. (CERN) ; Christensen, M.J. (ESS, Lund) ; Desch, K. (Bonn U.) ; Flöthner, K. (CERN ; Bonn U., HISKP) ; Garcia, F. (Helsinki U.) ; Hall-Wilton, R. (ESS, Lund ; Milan Bicocca U.) ; Hracek, M. (CERN ; Prague, Tech. U.) ; Iakovidis, G. (Brookhaven Natl. Lab.) ; Janssens, D. (CERN ; Vrije U., Brussels) ; Kaminski, J. (Bonn U.) ; Lupberger, M. (Bonn U. ; Bonn U., HISKP) ; Muller, H. (CERN ; Bonn U.) ; Oliveri, E. (CERN) ; Ropelewski, L. (CERN) ; Rusu, A. (CERN) ; Samarati, J. (ESS, Lund ; CERN) ; van Stenis, M. (CERN) ; Utrobicic, A. (CERN) ; Veenhof, R. (CERN ; Uludag U.)
Publication	2022-05-11
Imprint	2021-09-21
Number of pages	13
In:	Nucl. Instrum. Methods Phys. Res., A 1031 (2022) 166548
DOI	10.1016/j.nima.2022.166548 (publication)
Subject category	physics.ins-det ; Detectors and Experimental Techniques
Accelerator/Facility, Experiment	RD51
Abstract	The VMM3a is an Application Specific Integrated Circuit (ASIC), specifically developed for the readout of gaseous detectors. Originally developed within the ATLAS New Small Wheel (NSW) upgrade, it has been successfully integrated into the Scalable Readout System (SRS) of the RD51 collaboration. This allows, to use the VMM3a also in small laboratory set-ups and mid-scale experiments, which make use of Micro-Pattern Gaseous Detectors (MPGDs). As part of the integration of the VMM3a into the SRS, the readout and data transfer scheme was optimised to reach a high rate-capability of the entire readout system and profit from the VMM3a's high single-channel rate-capability of 3.6 Mhits/s. The optimisation focused mainly on the handling of the data output stream of the VMM3a, but also on the development of a trigger-logic between the front-end cards and the DAQ computer. In this article, two firmware implementations of the non-ATLAS continuous readout mode are presented, as well as the implementation of the trigger-logic. Afterwards, a short overview on X-ray imaging results is presented, to illustrate the high rate-capability rom an application point-of-view.
Copyright/License	publication: © 2022-2024 The Author(s) (License: CC BY 4.0) preprint: (License: CC BY 4.0)

$Timing diagram of the VMM3a in the non-ATLAS continuous readout mode. The Peak Detector (PDO) starts the $\SI{10}{bit}$ ADC for the charge information, and the voltage ramp (TAC slope) for the Time Detector (TDO). This voltage ramp is stopped by the next falling edge of the bunch crossing clock CKBC. The $\SI{8}{bit}$ value of the TDO represents thus the time between the peak and the subsequent BCID. To obtain the digitised data, a token is generated with the token clock CKTK, and passed around to channels with data. The channel that has the token is then bit-wise read out with the data clock CKDT on the two data lines \emph{data\textsubscript{0}} and \emph{data\textsubscript{1}}.$ Show more plots

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