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Article
Title Test results of ATLASPIX3 — A reticle size HVCMOS pixel sensor designed for construction of multi chip modules
Author(s) Schimassek, R. (KIT, Karlsruhe) ; Andreazza, A. (INFN, Milan ; Milan U.) ; Augustin, H. (Heidelberg U.) ; Barbero, M. (Marseille, CPPM) ; Benoit, M. (Geneva U.) ; Ehrler, F. (KIT, Karlsruhe) ; Iacobucci, G. (Geneva U.) ; Meneses, A. (Heidelberg U.) ; Pangaud, P. (Marseille, CPPM) ; Prathapan, M. (KIT, Karlsruhe) ; Schöning, A. (Heidelberg U.) ; Vilella, E. (Liverpool U.) ; Weber, A. (KIT, Karlsruhe ; Heidelberg U.) ; Weber, M. (Bern U.) ; Wong, W. (Geneva U.) ; Zhang, H. (KIT, Karlsruhe) ; Perić, I. (KIT, Karlsruhe)
Publication 2021
Published in: Nucl. Instrum. Methods. Phys. Res., A 986 (2021) 164812
Presented at 12th international "Hiroshima" Symposium on the Development and Application of Semiconductor Tracking Detectors (HSTD), Hiroshima, Japan, 14 - 18 Dec 2019, pp.164812
DOI 10.1016/j.nima.2020.164812
Accelerator/Facility, Experiment CERN-LHC-ATLAS
Abstract High voltage CMOS pixel sensors will be or are proposed to be used in several particle physics experiments for particle tracking like Mu3e experiment. ATLASPIX3 is the first full reticle size monolithic HVCMOS sensor for construction of multi-chip modules. The specifications for the use case have been taken from ATLAS pixel upgrade in fifth layer where it was a candidate for. The size of the chip is $2.0×2.1\mathrm{cm}^2$ with periphery at one side which makes the chip 3-side buttable. ATLASPIX3 has been implemented in a standard 180 nm HVCMOS process. Each pixel has an area of $150×50μ\mathrm{m}^2$ and contains a large charge collecting electrode implemented as deep n-well. The depleted volume around the n-well is enlarged by a high voltage bias and the usage of higher resistivity substrate. The readout electronics supports both triggered and triggerless readout with zero-suppression. ATLASPIX3 could be used for the construction of CMOS modules for particle tracking in experiments where high time resolution, high radiation tolerance, low power and low material budget are required. In the design phase, special attention has been paid to decreasing timing differences between pixels and the rate capability of the readout.
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 Δημιουργία εγγραφής 2020-11-11, τελευταία τροποποίηση 2020-11-11