| Početna stranica > A Verification Platform to provide the Functional, Characterization and Production testing for the VFAT3 ASIC |
| Published Articles | |
| Title | A Verification Platform to provide the Functional, Characterization and Production testing for the VFAT3 ASIC |
| Author(s) | Petrow, H (Lappeenranta U. Tech.) ; Aspell, P (CERN) ; Bravo, C (UCLA, Los Angeles (main)) ; Dabrowski, M (CERN) ; De Lentdecker, G (U. Brussels (main)) ; Leroux, P (Leuven U.) ; De Robertis, G (INFN, Bari) ; Irshad, A (Unlisted, PK) ; Lenzi, T (U. Brussels (main)) ; Licciulli, F (INFN, Bari) ; Loddo, F (INFN, Bari) ; Robert, F (U. Brussels (main)) ; Tavernier, F (Leuven U.) ; Rosa, J (U. Brussels (main)) ; Tuuva, T (Lappeenranta U. Tech.) |
| Publication | 2018 |
| Number of pages | 3 |
| In: | 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC 2017), Atlanta, Georgia, USA, 21 - 28 Oct 2017, pp.8532822 |
| DOI | 10.1109/NSSMIC.2017.8532822 |
| Subject category | Detectors and Experimental Techniques |
| Abstract | VFAT3 is a front-end ASIC designed for the readout of GEM detectors in the CMS Muon system. The strategy for the chip design was to design the full chip at once but provide extensive test and debug facilities for individual characterization of each internal chip module. The verification platform consists of three parts; namely the software (running on a PC), the firmware (designed for a Kintex-7 FPGA development board) and a selection of VFAT3 dedicated hardware boards for the different stages of verification. The system was designed to accommodate all of the steps needed to fully test the chip. The first step is the functional testing for which only rather simple functions are needed. For the functional testing. the software has an interactive interface to communicate with the chip through the FPGA. The requirements for the hardware are mostly the possibility for the use of the main communication channels. For the characterization of the chip, the software offers a possibility to easily generate lists of routine instructions that can be uploaded to the FPGA and run as synchronous commands. This allows for example the scanning of the chip's internal calibration DACs and creation of S-curves for all of the front-end channels. The hardware boards of the system allows access to the vast amount of test pads needed for the characterization and debug of the chip. The production tests require concatenated test routines where speed and execution efficiency are crucial. The software and the firmware of the system were designed to allow flexible evolution to increase the efficiency of complicated test routines. |