| Pàgina inicial > Scaling Procedures and Post-Optimization for the Design of High-Efficiency Klystrons |
| Article | |
| Title | Scaling Procedures and Post-Optimization for the Design of High-Efficiency Klystrons |
| Related title | Scaling Procedures and Post-Optimization for the Design of High-Efficiency Klystrons |
| Author(s) | Cai, Jinchi (CERN) ; Syratchev, Igor (CERN) ; Lui, Zening (Tsinghua U., Beijing) |
| Publication | 2019 |
| Number of pages | 7 |
| In: | IEEE Trans. Electron Devices 66 (2019) 1075-1081 |
| DOI | 10.1109/TED.2018.2887348 |
| Subject category | Accelerators and Storage Rings |
| Abstract | A semianalytical parametric scaling procedure (PSP) for klystron design has been developed. The PSP allows existing klystron designs to be scaled to different operating frequencies, beam power, and perveance, while maintaining the electron bunching and deceleration processes. For the fixed layout of a klystron RF circuit, the PSP provides parameters of the scaled klystron which are nearly optimal. The theoretical background and step by step derivation of the scaling principles are presented. The effectiveness of the PSP is shown through a generic five-cavity L-band klystron. |
| Copyright/License | publication: © 2018 IEEE (License: CC-BY-4.0) |