Title
| Simulations of busy probabilities in the ALPIDE chip and the upgraded ALICE ITS detector |
Author(s)
|
Nesbo, Simon Voigt (HVL, Norway) ; Alme, Johan (U. Bergen (main)) ; Bonora, Matthias (CERN) ; Giubilato, Piero (INFN, Padua ; Padua U.) ; Helstrup, Haavard (HVL, Norway) ; Hristozkov, Svetlomir (CERN) ; Aglieri Rinella, Gianluca (CERN) ; Röhrich, Dieter (U. Bergen (main)) ; Schambach, Joachim (U. Texas, Austin (main)) ; Shahoyan, Ruben (CERN) ; Ullaland, Kjetil (U. Bergen (main)) Show all 11 authors |
Collaboration
| ALICE ITS |
Publication
| SISSA, 2017 |
Number of pages
| 5 |
In:
| PoS TWEPP-17 (2017) 147 |
In:
| Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.147 |
DOI
| 10.22323/1.313.0147
|
Subject category
| Detectors and Experimental Techniques |
Accelerator/Facility, Experiment
| CERN LHC ; ALICE |
Abstract
| For the Long Shutdown 2 (LS2) upgrade of the ITS detector in the ALICE experiment at the LHC, a novel pixel detector chip, the ALPIDE chip, has been developed. In the event of busy ALPIDE chips in the ITS detector, the readout electronics may need to take appropriate action to minimize loss of data. This paper presents a lightweight, statistical simulation model for the ALPIDE chip and the up- graded ITS detector, developed using the SystemC framework. The purpose of the model is to quantify the probability of a busy condition and the data taking efficiency of the ALPIDE chips under various conditions, and to apply this knowledge during the development of the readout electronics and firmware. |
Copyright/License
| Copyright owned by the author(s) publication: (License: CC-BY-NC-ND-4.0) |