| Hovedsiden > LHCb Collection > LHCb Preprints > PACIFIC: the readout ASIC for the SciFi Tracker of the upgraded LHCb detector |
| Published Articles | |
| Title | PACIFIC: the readout ASIC for the SciFi Tracker of the upgraded LHCb detector |
| Author(s) | Mazorra, J (Valencia U., IFIC) ; Chanal, H (Clermont-Ferrand U.) ; Comerma, A (Heidelberg U.) ; Gascón, D (ICC, Barcelona U.) ; Gómez, S (ICC, Barcelona U.) ; Han, X (Heidelberg U.) ; Pillet, N (Clermont-Ferrand U.) ; Vandaele, R (Clermont-Ferrand U.) |
| Publication | 2016 |
| In: | JINST 11 (2016) C02021 |
| In: | Topical Workshop on Electronics for Particle Physics, Lisbon, Portugal, 28 Sep - 2 Oct 2015, pp.C02021 |
| DOI | 10.1088/1748-0221/11/02/C02021 |
| Subject category | Detectors and Experimental Techniques |
| Accelerator/Facility, Experiment | CERN LHC ; LHCb |
| Abstract | The LHCb detector will be upgraded during the Long Shutdown 2 (LS2) of the LHC in order to cope with higher instantaneous luminosities and will switch to a 40 MHz readout rate using a trigger-less software based system. All front-end electronics will be replaced and several sub-detectors must be redesigned to cope with the higher detector occupancy and radiation damage. The current tracking detectors downstream of the LHCb dipole magnet will be replaced by the Scintillating Fibre (SciFi) Tracker. The SciFi Tracker will use scintillating fibres read out by Silicon Photomultipliers (SiPMs). State-of-the-art multi-channel SiPM arrays are being developed and a custom ASIC, called the low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC), will be used to digitise the signals from the SiPMs. This article presents an overview of the R&D; for the PACIFIC. It is a 64-channel ASIC implemented in 130 nm CMOS technology, aiming at a radiation tolerant design with a power consumption below 10 mW per channel. It interfaces directly with the SiPM anode through a current mode input, and provides a configurable non-linear 2-bit per channel digital output. The SiPM signal is acquired by a current conveyor and processed with a fast shaper and a gated integrator. The digitization is performed using a three threshold non-linear flash ADC operating at 40 MHz. Simulation and test results show the PACIFIC chip prototypes functioning well. |