CERN Accelerating science

CMS Note
Report number	CMS-CR-2017-132
Title	Electronics for CMS Endcap Muon Level-1 Trigger System Phase-1 and HL LHC Upgrades Summary
Author(s)	Madorsky, Alexander (Florida U.)
Collaboration	CMS Collaboration
Publication	2017
Imprint	08 May 2017
Number of pages	7
In:	JINST 12 (2017) C07010
In:	Instrumentation for Colliding Beam Physics, Novosibirsk, Russia, 27 Feb - 3 Mar 2017, pp.C07010
DOI	10.1088/1748-0221/12/07/C07010
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; CMS
Abstract	To accommodate high-luminosity LHC operation at 13 TeV collision energy, the CMS Endcap Muon Level-1 Trigger system had to be significantly modified. To provide the best track reconstruction, the trigger system must now import all available trigger primitives generated by Cathode Strip Chambers and by certain other subsystems, such as Resistive Plate Chambers (RPC). In addition to massive input bandwidth, this also required significant increase in logic and memory resources.To satisfy these requirements, a new Sector Processor unit has been designed. It consists of three modules. The Core Logic module houses the large FPGA that contains the track-finding logic and multi-gigabit serial links for data exchange. The Optical module contains optical receivers and transmitters; it communicates with the Core Logic module via a custom backplane section. The Pt Lookup Table (PTLUT) module contains 1 GB of low-latency memory that is used to assign the final Pt to reconstructed muon tracks. The µTCA architecture (adopted by CMS) was used for this design. The talk presents the details of the hardware and firmware design of the production system based on Xilinx Virtex-7 FPGA family. The next round of LHC and CMS upgrades starts in 2019, followed by a major High-Luminosity (HL) LHC upgrade starting in 2024. In the course of these upgrades, the new Gas Electron Multiplier (GEM) detector and more RPC chambers will be added to the Endcap Muon system. In order to keep up with all these changes, a new Advanced Processor unit is being designed. This device will be based on Xilinx UltraScale+ FPGAs. It will be able to accommodate up to 100 serial links with bit rates of up to 25 Gb/s, and provide up to 2.5 times more logic resources than the device used currently. The amount of PTLUT memory will be significantly increased to provide more flexibility for Pt assignment algorithm. The talk presents preliminary details of the hardware design program.
Copyright/License	Preprint: (License: CC-BY-4.0)

Corresponding record in: Inspire