CERN Accelerating science

Published Articles
Title Highly parallelized pattern matching execution for the ATLAS experiment
Author(s) Annovi, A (INFN, Pisa) ; Bertolucci, F (INFN, Pisa) ; Biesuz, N (Pisa U.) ; Calabro, D (INFN, Pavia) ; Calderini, G (Paris U., VI-VII) ; Citraro, S (Pisa U.) ; Crescioli, F (Paris U., VI-VII) ; Dimas, D (Prisma Electronics SA, Athens) ; Dell'Orso, M (Pisa U.) ; Donati, S (Pisa U.) ; Gentsos, C (Aristotle U., Thessaloniki) ; Giannetti, P (INFN, Pisa) ; Gkaitatzis, S (Aristotle U., Thessaloniki) ; Greco, V (CERN) ; Kalaitzidis, P (Prisma Electronics SA, Athens) ; Kordas, K (Aristotle U., Thessaloniki) ; Kimura, N (Aristotle U., Thessaloniki) ; Kubota, T (Melbourne U.) ; Lanza, A (INFN, Pavia) ; Luciano, P (INFN, Pisa) ; Magnin, B (CERN) ; Maznas, I (Aristotle U., Thessaloniki) ; Mermikli, K (Prisma Electronics SA, Athens) ; Nasimi, H (Pisa U.) ; Nikolaidis, S (Aristotle U., Thessaloniki) ; Piendibene, M (Pisa U.) ; Sakellariou, A (Prisma Electronics SA, Athens) ; Sampsonidis, D (Aristotle U., Thessaloniki) ; Sotiropoulou, C L (Pisa U.) ; Volpi, G (INFN, Pisa) ; Xiotidis, I (Aristotle U., Thessaloniki)
Publication 2016
Number of pages 3
In: 2015 IEEE Nuclear Science Symposium and Medical Imaging Conference, San Diego, CA, USA, 31 Oct - 7 Nov 2015, pp.7581789
DOI 10.1109/NSSMIC.2015.7581789
Subject category Detectors and Experimental Techniques
Accelerator/Facility, Experiment CERN LHC ; ATLAS
Abstract The Associative Memory (AM) system of the Fast TracKer (FTK) processor has been designed to perform pattern matching using as input the data from the silicon tracker in the ATLAS experiment. The AM is the primary component of the FTK system and is designed using ASIC technology (the AM chip) to execute pattern matching with a high degree of parallelism. The FTK system finds track candidates at low resolution that are seeds for a full resolution track fitting. The AM system implementation is named “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links to sustain a huge traffic of data. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Little Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME motherboard which hosts four LAMB daughterboards. We also report on the performance of the prototypes (both hardware and firmware) produced and tested in the global FTK integration, an important milestone to be satisfied before the FTK production.

Corresponding record in: Inspire


 Записът е създаден на 2017-05-12, последна промяна на 2017-07-31