CERN Accelerating science

ATLAS Note
Report number	ATL-TILECAL-PROC-2017-003
Title	A TTC to Data Acquisition interface for the ATLAS Tile Hadronic calorimeter at the LHC
Author(s)	Valero, Alberto (Instituto de Fisica Corpuscular (IFIC), Centro Mixto Universidad de Valencia - CSIC) ; Garcia Aparisi, Francisco Brandan (Instituto de Fisica Corpuscular (IFIC), Centro Mixto Universidad de Valencia - CSIC) ; Torres Pais, Jose Gabriel (Instituto de Fisica Corpuscular (IFIC), Centro Mixto Universidad de Valencia - CSIC) ; Soret Medel, Jesús (Instituto de Fisica Corpuscular (IFIC), Centro Mixto Universidad de Valencia - CSIC) ; Garcia Olcina, Raimundo (Instituto de Fisica Corpuscular (IFIC), Centro Mixto Universidad de Valencia - CSIC) ; Martos Torres, Julio (Instituto de Fisica Corpuscular (IFIC), Centro Mixto Universidad de Valencia - CSIC) ; Fiorini, Luca (Instituto de Fisica Corpuscular (IFIC), Centro Mixto Universidad de Valencia - CSIC) ; Carrio Argos, Fernando (Instituto de Fisica Corpuscular (IFIC), Centro Mixto Universidad de Valencia - CSIC) ; Valls Ferrer, Juan Antonio (Instituto de Fisica Corpuscular (IFIC), Centro Mixto Universidad de Valencia - CSIC) ; Zuccarello, Pedro Diego (Instituto de Fisica Corpuscular (IFIC), Centro Mixto Universidad de Valencia - CSIC)
Corporate Author(s)	The ATLAS collaboration
Collaboration	ATLAS Collaboration
Publication	2017
Imprint	05 Apr 2017
Number of pages	4
Subject category	Particle Physics - Experiment
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Free keywords	FPGA ; VME ; TTC
Abstract	TileCal is the central tile hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN. It is a sampling calorimeter where scintillating tiles are embedded in steel absorber plates. The tiles are read-out using almost 10,000 photomultipliers which convert the light into an electrical signal. These signals are digitized and stored in pipelines memories in the front-end electronics. Upon the reception of a trigger signal, the PMT data is transferred to the Read-Out Drivers in the back-end electronics which process and transmits the processed data to the ATLAS Data AcQuisition (DAQ) system. The Timing, Trigger and Control (TTC) system is an optical network used to distribute the clock synchronized with the accelerator, the trigger signals and configuration commands to both the front-end and back-end electronics components. During physics operation, the TTC system is used to configure the electronics and to distribute trigger information used to synchronize the different parts of the readout chain. This information includes event identification, synchronization signals and configuration and calibration commands. The TDI (TTC to DAQ Interface) is a VME 6U module able to receive and decode the TTC information and transmit it to the DAQ system. The input stage is an optical receiver connected to a Xilinx Spartan 6 FPGA, called CentralFPGA. The CentralFPGA decodes the TTC commands and recovers the LHC clock using an ADN2814 chip from Analog devices. The data is stored in internal buffers implemented in the CentralFPGA and transmitted through the VME bus to the DAQ software application through regular GPIOs. In addition, the DAQ software can be also reached through an Ethernet port in the front panel. Finally, the TDI module is able to transmit signals to the trigger system to stop the generation of trigger signals in case the internal buffers are full. The system functionalities and communication protocols are all implemented in firmware in the CentralFPGA which allows future functionalities upgrades. The TDI is particularly important during calibration runs to decode and store the configuration used on every processed event. In this contribution we present the components and interfaces of the TDI module, the main functionalities and a detailed description of the board design and firmware developments.
Copyright/License	Preprint: (License: CC-BY-4.0)