| Article | |
| Title | NaNet-10: a 10GbE network interface card for the GPU-based low-level trigger of the NA62 RICH detector |
| Author(s) | Ammendola, R (INFN, Rome2) ; Biagioni, A (INFN, Rome) ; Fiorini, M (Ferrara U. ; INFN, Ferrara) ; Frezza, O (INFN, Rome) ; Lonardo, A (INFN, Rome ; CERN) ; Lamanna, G (Frascati) ; Cicero, F Lo (INFN, Rome) ; Martinelli, M (INFN, Rome) ; Neri, I (Ferrara U. ; INFN, Ferrara) ; Paolucci, P S (INFN, Rome) ; Pastorelli, E (INFN, Rome) ; Piandani, R (INFN, Pisa) ; Pontisso, L (INFN, Pisa) ; Rossetti, D (Unlisted, US, CA) ; Simula, F (INFN, Rome) ; Sozzi, M (INFN, Pisa) ; Tosoratto, L (INFN, Rome) ; Vicini, P (INFN, Rome) |
| Publication | 2016 |
| Number of pages | 10 |
| In: | JINST 11 (2016) C03030 |
| In: | Topical Workshop on Electronics for Particle Physics, Lisbon, Portugal, 28 Sep - 2 Oct 2015, pp.C03030 |
| DOI | 10.1088/1748-0221/11/03/C03030 |
| Subject category | Detectors and Experimental Techniques |
| Accelerator/Facility, Experiment | CERN SPS ; NA62 |
| Abstract | A GPU-based low level (L0) trigger is currently integrated in the experimental setup of the RICH detector of the NA62 experiment to assess the feasibility of building more refined physics-related trigger primitives and thus improve the trigger discriminating power. To ensure the real-time operation of the system, a dedicated data transport mechanism has been implemented: an FPGA-based Network Interface Card (NaNet-10) receives data from detectors and forwards them with low, predictable latency to the memory of the GPU performing the trigger algorithms. Results of the ring-shaped hit patterns reconstruction will be reported and discussed. |
| Copyright/License | publication: © 2016-2025 The Author(s) (License: CC-BY-3.0) |
Corresponding record in: Inspire
Record created 2017-02-24, last modified 2022-08-10
