CERN Accelerating science

ATLAS Note
Report number	ATL-DAQ-PROC-2015-059
Title	gFEX, the ATLAS Calorimeter Level-1 Real Time Processor
Author(s)	Tang, Shaochun (Brookhaven National Laboratory (BNL)) ; Begel, Michael (Brookhaven National Laboratory (BNL)) ; Chen, Hucheng (Brookhaven National Laboratory (BNL)) ; Lanni, Francesco (Brookhaven National Laboratory (BNL)) ; Takai, Helio (Brookhaven National Laboratory (BNL)) ; Wu, Weihao (Brookhaven National Laboratory (BNL))
Corporate Author(s)	The ATLAS collaboration
Publication	2016
Imprint	20 Nov 2015
Number of pages	5
In:	2015 IEEE Nuclear Science Symposium and Medical Imaging Conference, San Diego, CA, USA, 31 Oct - 7 Nov 2015, pp.7581865
DOI	10.1109/NSSMIC.2015.7581865
Subject category	Particle Physics - Experiment
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Free keywords	gFEX
Abstract	The global feature extractor (gFEX) is a component of the Level-1 Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Vertex Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 276 optical fibers with the data transferred at the 40 MHz Large Hadron Collider (LHC) clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor Field-Programmable Gate Array (FPGAs), monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA has been designed for testing and verification. After the elementary technologies have been verified in the pre-prototype, a more advanced prototype with three Vertex Ultra-scale FPGAs is being designed. Although the board is being designed specifically for the ATLAS experiment, it is sufficiently generic that it could be used for fast data processing at other HEP or NP experiments.
Copyright/License	Preprint: (License: CC-BY-4.0)

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