CERN Accelerating science

CMS Note
Report number	CMS-CR-2015-063
Title	A New Event Builder for CMS Run II
Author(s)	Albertsson, Kim (CERN) ; Andre, Jean-marc Olivier (Fermilab) ; Andronidis, Anastasios (Ioannina U.) ; Behrens, Ulf (DESY) ; Branson, James (UC, San Diego) ; Chaze, Olivier (CERN) ; Cittolin, Sergio (UC, San Diego) ; Darlea, Georgiana Lavinia (MIT) ; Deldicque, Christian (CERN) ; Dobson, Marc (CERN) ; Dupont, Aymeric (CERN) ; Erhan, Samim (UCLA) ; Gigi, Dominique (CERN) ; Glege, Frank (CERN) ; Gomez Ceballos, Guillelmo (MIT) ; Hegeman, Jeroen Guido (CERN) ; Holzner, Andre Georg (UC, San Diego) ; Jimenez Estupinan, Raul (CERN) ; Masetti, Lorenzo (CERN) ; Meijers, Franciscus (CERN) ; Meschi, Emilio (CERN) ; Mommsen, Remigius (Fermilab) ; Morovic, Srecko (CERN) ; Nunez Barranco Fernandez, Carlos (CERN) ; O'Dell, Vivian (Fermilab) ; Orsini, Luciano (CERN) ; Paus, Christoph Maria Ernst (MIT) ; Petrucci, Andrea (CERN) ; Pieri, Marco (UC, San Diego) ; Racz, Attila (CERN) ; Roberts, Penelope Amelia (CERN) ; Sakulin, Hannes (CERN) ; Schwick, Christoph (CERN) ; Stieger, Benjamin Bastian (CERN) ; Sumorok, Konstanty (MIT) ; Veverka, Jan (MIT) ; Zaza, Salvatore (CERN) ; Zejdl, Petr (Fermilab)
Publication	2015
Imprint	12 May 2015
Number of pages	9
In:	J. Phys.: Conf. Ser. 664 (2015) 082035
In:	21st International Conference on Computing in High Energy and Nuclear Physics, Okinawa, Japan, 13 - 17 Apr 2015, pp.082035
DOI	10.1088/1742-6596/664/8/082035
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; CMS
Abstract	The data acquisition system (DAQ) of the CMS experiment at the CERN Large Hadron Collider (LHC) assembles events at a rate of 100kHz, transporting event data at an aggregate throughput of 100GB/s to the high-level trigger (HLT) farm. The DAQ system has been redesigned during the LHC shutdown in 2013/14. The new DAQ architecture is based on state-of-the-art network technologies for the event building. For the data concentration, 10/40Gbps Ethernet technologies are used together with a reduced TCP/IP protocol implemented in FPGA for a reliable transport between custom electronics and commercial computing hardware. A 56Gbps Infiniband FDR CLOS network has been chosen for the event builder. This paper discusses the software design, protocols, and optimizations for exploiting the hardware capabilities. We present performance measurements from small-scale prototypes and from the full-scale production system.
Copyright/License	publication: © 2015-2025 The Author(s), © 2015-2025 The Author(s) (Licenses: CC-BY-3.0, CC-BY-3.0)

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